URL
https://opencores.org/ocsvn/raptor64/raptor64/trunk
[/] [raptor64/] [trunk/] [rtl/] [verilog/] [Raptor64_dcache_ram.v] - Diff between revs 48 and 50
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| Rev 48 |
Rev 50 |
| Line 49... |
Line 49... |
always @(posedge rclk)
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always @(posedge rclk)
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rradr <= radr[14:3];
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rradr <= radr[14:3];
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assign o = mem[rradr];
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assign o = mem[rradr];
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/*
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endmodule
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syncRam2kx8_1rw1r u1
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[0] && !wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[7:0]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[7:0])
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);
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syncRam2kx8_1rw1r u2
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[1] && !wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[15:8]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[15:8])
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);
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syncRam2kx8_1rw1r u3
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[2] && !wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[23:16]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[23:16])
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);
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syncRam2kx8_1rw1r u4
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[3] && !wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[31:24]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[31:24])
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);
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syncRam2kx8_1rw1r u5
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[0] && wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[7:0]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[39:32])
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);
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syncRam2kx8_1rw1r u6
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[1] && wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[15:8]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[47:40])
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);
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syncRam2kx8_1rw1r u7
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[2] && wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[23:16]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[55:48])
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);
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syncRam2kx8_1rw1r u8
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(
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.wrst(1'b0),
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.wclk(clk),
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.wce(sel[3] && wadr[2]),
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.we(wr),
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.wadr(wadr[13:3]),
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.i(i[31:24]),
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.wo(),
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.rrst(1'b0),
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.rclk(~clk),
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.rce(1'b1),
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.radr(radr[13:3]),
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.o(o[63:56])
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);
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*/endmodule
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