| Line 111... |
Line 111... |
reg [31:0] dIR,xIR,m1IR,m2IR,wIR;
|
reg [31:0] dIR,xIR,m1IR,m2IR,wIR;
|
reg [31:0] ndIR; // next dIR
|
reg [31:0] ndIR; // next dIR
|
reg [63:0] pc;
|
reg [63:0] pc;
|
wire [63:0] pchistoric;
|
wire [63:0] pchistoric;
|
reg pccap;
|
reg pccap;
|
reg [63:0] ErrorEPC,EPC,IPC;
|
reg [63:0] ErrorEPC;
|
|
reg [63:0] EPC [0:15];
|
|
reg [63:0] IPC [0:15];
|
reg [63:0] dpc,xpc,m1pc,m2pc,wpc;
|
reg [63:0] dpc,xpc,m1pc,m2pc,wpc;
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
reg dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
|
wire [63:0] rfoa,rfob,rfoc;
|
wire [63:0] rfoa,rfob,rfoc;
|
wire [8:0] dRa,dRb,dRc;
|
wire [8:0] dRa,dRb,dRc;
|
reg [8:0] wRt,m1Rt,m2Rt,tRt;
|
reg [8:0] wRt,m1Rt,m2Rt,tRt;
|
| Line 124... |
Line 126... |
reg [63:0] ea;
|
reg [63:0] ea;
|
reg [4:0] cstate;
|
reg [4:0] cstate;
|
reg dbranch_taken,xbranch_taken;
|
reg dbranch_taken,xbranch_taken;
|
reg [63:0] mutex_gate;
|
reg [63:0] mutex_gate;
|
reg [63:0] TBA; // Trap Base Address
|
reg [63:0] TBA; // Trap Base Address
|
reg [1:0] dhwxtype,xhwxtype,m1hwxtype,m2hwxtype,whwxtype;
|
|
reg [8:0] dextype,xextype,m1extype,m2extype,wextype,textype;
|
reg [8:0] dextype,xextype,m1extype,m2extype,wextype,textype;
|
reg [3:0] epat [0:255];
|
reg [3:0] epat [0:255];
|
reg [7:0] eptr;
|
reg [7:0] eptr;
|
reg [3:0] dAXC,xAXC,m1AXC,m2AXC;
|
reg [3:0] dAXC,xAXC,m1AXC,m2AXC,wAXC;
|
wire [3:0] AXC = epat[eptr];
|
wire [3:0] AXC = epat[eptr];
|
reg dtinit;
|
reg dtinit;
|
reg dcache_on;
|
reg dcache_on;
|
reg [63:32] nonICacheSeg;
|
reg [63:32] nonICacheSeg;
|
reg [1:0] FPC_rm;
|
reg [1:0] FPC_rm;
|
| Line 191... |
Line 192... |
reg xirqf;
|
reg xirqf;
|
wire advanceX_edge;
|
wire advanceX_edge;
|
wire takb;
|
wire takb;
|
wire advanceX,advanceM1,advanceW;
|
wire advanceX,advanceM1,advanceW;
|
reg m1IsLoad,m2IsLoad;
|
reg m1IsLoad,m2IsLoad;
|
reg m1IsIO;
|
//reg m1IsIO;
|
reg m1IsStore,m2IsStore,wIsStore;
|
reg m1IsStore,m2IsStore,wIsStore;
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg cyc1;
|
reg cyc1;
|
reg LoadNOPs;
|
reg LoadNOPs;
|
| Line 332... |
Line 333... |
|
|
// SYSCALL 509
|
// SYSCALL 509
|
wire syscall509 = 32'b0000000_11000_0000_11111110_10010111;
|
wire syscall509 = 32'b0000000_11000_0000_11111110_10010111;
|
wire [63:0] bevect = {syscall509,syscall509};
|
wire [63:0] bevect = {syscall509,syscall509};
|
|
|
|
// Xilinx Core Generator Component
|
Raptor64_icache_ram u1
|
Raptor64_icache_ram u1
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.wea(icaccess & (ack_i|err_i)), // input [0 : 0] wea
|
.wea(icaccess & (ack_i|err_i)), // input [0 : 0] wea
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
.addra(adr_o[12:3]), // input [9 : 0] addra
|
| Line 391... |
Line 393... |
wire [64:15] dtgout;
|
wire [64:15] dtgout;
|
reg wrhit;
|
reg wrhit;
|
reg wr_dcache;
|
reg wr_dcache;
|
|
|
// cache RAM 32Kb
|
// cache RAM 32Kb
|
|
// Xilinx Core Generator Component
|
Raptor64_dcache_ram u10
|
Raptor64_dcache_ram u10
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.ena(1'b1),
|
.ena(1'b1),
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
| Line 405... |
Line 408... |
.addrb(pea[14:3]), // input [11 : 0] addrb
|
.addrb(pea[14:3]), // input [11 : 0] addrb
|
.doutb(cdat) // output [63 : 0] doutb
|
.doutb(cdat) // output [63 : 0] doutb
|
);
|
);
|
|
|
|
|
|
// Xilinx Core Generator Component
|
|
// tag RAM 512 b
|
Raptor64_dcache_tagram u11
|
Raptor64_dcache_tagram u11
|
(
|
(
|
.clka(clk), // input clka
|
.clka(clk), // input clka
|
.ena(dtinit | (adr_o[5:3]==3'b111)), // input ena
|
.ena(dtinit | (adr_o[5:3]==3'b111)), // input ena
|
.wea(dtinit | (dcaccess & ack_i)), // input [0 : 0] wea
|
.wea(dtinit | (dcaccess & ack_i)), // input [0 : 0] wea
|
.addra({1'b0,adr_o[14:6]}), // input [9 : 0] addra
|
.addra(adr_o[14:6]), // input [8 : 0] addra
|
.dina(dtinit ? {1'b0,adr_o[63:15]} : {1'b1,adr_o[63:15]}), // input [48 : 0] dina
|
.dina({~dtinit,adr_o[63:15]}), // input [49 : 0] dina
|
|
|
.clkb(~clk), // input clkb
|
.clkb(~clk), // input clkb
|
.addrb({1'b0,pea[14:6]}), // input [9 : 0] addrb
|
.addrb(pea[14:6]), // input [8 : 0] addrb
|
.doutb(dtgout) // output [48 : 0] doutb
|
.doutb(dtgout) // output [49 : 0] doutb
|
);
|
);
|
|
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 533... |
Line 538... |
wire f2i_ovr,fpmul_ovr,fpdiv_ovr,fpaddsub_ovr;
|
wire f2i_ovr,fpmul_ovr,fpdiv_ovr,fpaddsub_ovr;
|
wire fpmul_uf,fpaddsub_uf,fpdiv_uf;
|
wire fpmul_uf,fpaddsub_uf,fpdiv_uf;
|
|
|
|
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
|
// Xilinx Core Generator Components
|
|
|
Raptor64_fpCmp u60
|
Raptor64_fpCmp u60
|
(
|
(
|
.a(a), // input [63 : 0] a
|
.a(a), // input [63 : 0] a
|
.b(b), // input [63 : 0] b
|
.b(b), // input [63 : 0] b
|
| Line 607... |
Line 613... |
if (fltdone) begin
|
if (fltdone) begin
|
FPC_overx <= fp_ovr;
|
FPC_overx <= fp_ovr;
|
end
|
end
|
if (advanceX) begin
|
if (advanceX) begin
|
if (xOpcode==`FP) begin
|
if (xOpcode==`FP) begin
|
if (xFunc6==6'b000000) // FDADD
|
if (xFunc6==`FDADD) // FDADD
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==6'b000001) // FDSUB
|
else if (xFunc6==`FDSUB) // FDSUB
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==6'b000010) // FDMUL
|
else if (xFunc6==`FDMUL) // FDMUL
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==6'b000011) // FDDIV
|
else if (xFunc6==`FDDIV) // FDDIV
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==6'b000100) // unordered
|
else if (xFunc6==6'b000100) // unordered
|
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
else if (xFunc6==6'b001100) // less than
|
else if (xFunc6==6'b001100) // less than
|
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
| Line 629... |
Line 635... |
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
else if (xFunc6==6'b101100) // not equal
|
else if (xFunc6==6'b101100) // not equal
|
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
else if (xFunc6==6'b110100) // greater than or equal
|
else if (xFunc6==6'b110100) // greater than or equal
|
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
else if (xFunc6==6'b000101) // ItoFD
|
else if (xFunc6==`FDI2F) // ItoFD
|
fltctr <= 6'd7;
|
fltctr <= 6'd7;
|
else if (xFunc6==6'b000110) // FFtoI
|
else if (xFunc6==6'b000110) // FFtoI
|
fltctr <= 6'd6;
|
fltctr <= 6'd6;
|
else if (xFunc6==6'b000111) // FtoD
|
else if (xFunc6==6'b000111) // FtoD
|
fltctr <= 6'd2;
|
fltctr <= 6'd2;
|
| Line 797... |
Line 803... |
wire [15:0] bcdmulo;
|
wire [15:0] bcdmulo;
|
|
|
Raptor64_addsub u21 (xIR,a,b,imm,xAddsubo);
|
Raptor64_addsub u21 (xIR,a,b,imm,xAddsubo);
|
Raptor64_logic u9 (xIR,a,b,imm,xLogico);
|
Raptor64_logic u9 (xIR,a,b,imm,xLogico);
|
Raptor64_set u15 (xIR,a,b,imm,xSeto);
|
Raptor64_set u15 (xIR,a,b,imm,xSeto);
|
Raptor64_bitfield u16(xIR, rolo, b, xBitfieldo, masko);
|
Raptor64_bitfield u16(xIR, a, b, xBitfieldo, masko);
|
Raptor64_shift u17 (xIR, a, b, masko, xShifto, rolo);
|
Raptor64_shift u17 (xIR, a, b, masko, xShifto, rolo);
|
BCDMul2 u22 (a[7:0],b[7:0],bcdmulo);
|
BCDMul2 u22 (a[7:0],b[7:0],bcdmulo);
|
|
|
wire aeqz = a==64'd0;
|
wire aeqz = a==64'd0;
|
wire eq = a==b;
|
wire eq = a==b;
|
| Line 830... |
Line 836... |
`ABS: xData1 = a[63] ? -a : a;
|
`ABS: xData1 = a[63] ? -a : a;
|
`SGN: xData1 = a[63] ? 64'hFFFFFFFF_FFFFFFFF : aeqz ? 64'd0 : 64'd1;
|
`SGN: xData1 = a[63] ? 64'hFFFFFFFF_FFFFFFFF : aeqz ? 64'd0 : 64'd1;
|
`MOV: xData1 = a;
|
`MOV: xData1 = a;
|
`SQRT: xData1 = sqrt_out;
|
`SQRT: xData1 = sqrt_out;
|
`SWAP: xData1 = {a[31:0],a[63:32]};
|
`SWAP: xData1 = {a[31:0],a[63:32]};
|
|
`RBO: xData1 = {a[7:0],a[15:8],a[23:16],a[31:24],a[39:32],a[47:40],a[55:48],a[63:56]};
|
|
|
`REDOR: xData1 = |a;
|
`REDOR: xData1 = |a;
|
`REDAND: xData1 = &a;
|
`REDAND: xData1 = &a;
|
|
|
`CTLZ: xData1 = cntlzo;
|
`CTLZ: xData1 = cntlzo;
|
| Line 875... |
Line 882... |
`PageTableAddr: xData1 = {PageTableAddr,13'd0};
|
`PageTableAddr: xData1 = {PageTableAddr,13'd0};
|
`BadVAddr: xData1 = {BadVAddr,13'd0};
|
`BadVAddr: xData1 = {BadVAddr,13'd0};
|
`endif
|
`endif
|
`ASID: xData1 = ASID;
|
`ASID: xData1 = ASID;
|
`Tick: xData1 = tick;
|
`Tick: xData1 = tick;
|
`EPC: xData1 = EPC;
|
`EPC: xData1 = EPC[xAXC];
|
`IPC: xData1 = IPC;
|
`IPC: xData1 = IPC[xAXC];
|
`TBA: xData1 = TBA;
|
`TBA: xData1 = TBA;
|
`ERRADR: xData1 = errorAddress;
|
`ERRADR: xData1 = errorAddress;
|
`AXC: xData1 = xAXC;
|
`AXC: xData1 = xAXC;
|
`NON_ICACHE_SEG: xData1 = nonICacheSeg;
|
`NON_ICACHE_SEG: xData1 = nonICacheSeg;
|
`FPCR: xData1 = FPC;
|
`FPCR: xData1 = FPC;
|
| Line 943... |
Line 950... |
xData1 = a + imm;
|
xData1 = a + imm;
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
`OUTB,`OUTC,`OUTH,`OUTW:
|
xData1 = a + imm;
|
xData1 = a + imm;
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR,`LF,`LFD,`LP,`LFP,`LFDP,`LEA:
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LWR,`LF,`LFD,`LP,`LFP,`LFDP,`LEA:
|
xData1 = a + imm;
|
xData1 = a + imm;
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SP,`SFP,`SFDP:
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SP,`SFP,`SFDP,`STBC:
|
xData1 = a + imm;
|
xData1 = a + imm;
|
`MEMNDX:
|
`MEMNDX:
|
xData1 = a + (b << scale) + imm;
|
xData1 = a + (b << scale) + imm;
|
`TRAPcc: xData1 = fnIncPC(xpc);
|
`TRAPcc: xData1 = fnIncPC(xpc);
|
`TRAPcci: xData1 = fnIncPC(xpc);
|
`TRAPcci: xData1 = fnIncPC(xpc);
|
| Line 985... |
Line 992... |
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xAddsubo[63]), .v(v_ri));
|
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xAddsubo[63]), .v(v_ri));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xAddsubo[63]), .v(v_rr));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xAddsubo[63]), .v(v_rr));
|
|
|
wire dbz_error = ((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc6==`DIVS || xFunc6==`DIVU) && b==64'd0);
|
wire dbz_error = ((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc6==`DIVS || xFunc6==`DIVU) && b==64'd0);
|
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc6==`SUB || xFunc6==`ADD)) && v_rr);
|
wire ovr_error = ((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc6==`SUB || xFunc6==`ADD)) && v_rr);
|
|
// ToDo: add more priv violations
|
wire priv_violation = !KernelMode && (xOpcode==`MISC &&
|
wire priv_violation = !KernelMode && (xOpcode==`MISC &&
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI || xFunc==`IEPP
|
));
|
));
|
wire illegal_insn = (xOpcode==7'd19 || xOpcode==7'd47 || xOpcode==7'd54 || xOpcode==7'd55 || xOpcode==7'd63 || xOpcode==7'd71 ||
|
// ToDo: detect illegal instructions in the hives (sub-opcodes)
|
xOpcode==7'd90 || xOpcode==7'd91 || xOpcode==7'd92 || xOpcode==7'd93 || xOpcode==7'd106 || xOpcode==7'd107)
|
wire illegal_insn = (
|
|
xOpcode==7'd19 ||
|
|
xOpcode==7'd20 ||
|
|
xOpcode==7'd28 ||
|
|
xOpcode==7'd29 ||
|
|
xOpcode==7'd30 ||
|
|
xOpcode==7'd31 ||
|
|
xOpcode==7'd47 ||
|
|
xOpcode==7'd54 ||
|
|
xOpcode==7'd55 ||
|
|
xOpcode==7'd63 ||
|
|
xOpcode==7'd71 ||
|
|
xOpcode==7'd90 ||
|
|
xOpcode==7'd91 ||
|
|
xOpcode==7'd92 ||
|
|
xOpcode==7'd93 ||
|
|
xOpcode==7'd106 ||
|
|
xOpcode==7'd107 ||
|
|
xOpcode==7'd124 ||
|
|
xOpcode==7'd125 ||
|
|
xOpcode==7'd126 ||
|
|
xOpcode==7'd127
|
|
)
|
;
|
;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
// For performance and core size reasons, the following should really decode
|
|
// the opcodes in the decode stage, then pass the decoding information forward
|
|
// using regs. However the core is trickier to get working that way; decoding
|
|
// in multiple stages is simpler.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//wire dIsLoad =
|
//wire dIsLoad =
|
// dOpcode==`LW || dOpcode==`LH || dOpcode==`LB || dOpcode==`LWR ||
|
// dOpcode==`LW || dOpcode==`LH || dOpcode==`LB || dOpcode==`LWR ||
|
// dOpcode==`LHU || dOpcode==`LBU ||
|
// dOpcode==`LHU || dOpcode==`LBU ||
|
// dOpcode==`LC || dOpcode==`LCU || dOpcode==`LM ||
|
// dOpcode==`LC || dOpcode==`LCU || dOpcode==`LM ||
|
| Line 1044... |
Line 1078... |
wire xIsMult = (xOpcode==`RR && (xFunc6==`MULU || xFunc6==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI;
|
wire xIsMult = (xOpcode==`RR && (xFunc6==`MULU || xFunc6==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI;
|
wire xIsDiv = (xOpcode==`RR && (xFunc6==`DIVU || xFunc6==`DIVS || xFunc6==`MODU || xFunc6==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI;
|
wire xIsDiv = (xOpcode==`RR && (xFunc6==`DIVU || xFunc6==`DIVS || xFunc6==`MODU || xFunc6==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI;
|
wire xIsCnt = xOpcode==`R && (xFunc6==`CTLZ || xFunc6==`CTLO || xFunc6==`CTPOP);
|
wire xIsCnt = xOpcode==`R && (xFunc6==`CTLZ || xFunc6==`CTLO || xFunc6==`CTPOP);
|
reg m1IsCnt,m2IsCnt;
|
reg m1IsCnt,m2IsCnt;
|
|
|
|
// Have to set the xIsLoad/xIsStore flag to false when xIR is nopped out
|
wire xIsLoad =
|
wire xIsLoad =
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`LF || xOpcode==`LFD || xOpcode==`LP || xOpcode==`LFP || xOpcode==`LFDP ||
|
xOpcode==`LF || xOpcode==`LFD || xOpcode==`LP || xOpcode==`LFP || xOpcode==`LFDP ||
|
| Line 1060... |
Line 1094... |
xFunc6==`LFX || xFunc6==`LFDX || xFunc6==`LPX ||
|
xFunc6==`LFX || xFunc6==`LFDX || xFunc6==`LPX ||
|
xFunc6==`LSHX || xFunc6==`LSWX
|
xFunc6==`LSHX || xFunc6==`LSWX
|
)) ||
|
)) ||
|
(xOpcode==`MISC && (xFunc==`SYSCALL))
|
(xOpcode==`MISC && (xFunc==`SYSCALL))
|
;
|
;
|
|
|
wire xIsStore =
|
wire xIsStore =
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SSH || xOpcode==`SSW ||
|
xOpcode==`SSH || xOpcode==`SSW || xOpcode==`STBC ||
|
(xOpcode==`MEMNDX && (
|
(xOpcode==`MEMNDX && (
|
xFunc6==`SWX || xFunc6==`SHX || xFunc6==`SBX || xFunc6==`SCX || xFunc6==`SWCX ||
|
xFunc6==`SWX || xFunc6==`SHX || xFunc6==`SBX || xFunc6==`SCX || xFunc6==`SWCX ||
|
xFunc6==`SFX || xFunc6==`SFDX || xFunc6==`SPX ||
|
xFunc6==`SFX || xFunc6==`SFDX || xFunc6==`SPX ||
|
xFunc6==`SSHX || xFunc6==`SSWX
|
xFunc6==`SSHX || xFunc6==`SSWX
|
))
|
))
|
| Line 1097... |
Line 1130... |
(m1Opcode==`MEMNDX && (
|
(m1Opcode==`MEMNDX && (
|
m1Func6==`INWX || m1Func6==`INHX || m1Func6==`INCX || m1Func6==`INBX ||
|
m1Func6==`INWX || m1Func6==`INHX || m1Func6==`INCX || m1Func6==`INBX ||
|
m1Func6==`INHUX || m1Func6==`INCUX || m1Func6==`INBUX
|
m1Func6==`INHUX || m1Func6==`INCUX || m1Func6==`INBUX
|
))
|
))
|
;
|
;
|
|
wire m1IsOut = m1Opcode==`OUTW || m1Opcode==`OUTH || m1Opcode==`OUTC || m1Opcode==`OUTB ||
|
|
(m1Opcode==`MEMNDX && (
|
|
m1Func6==`OUTWX || m1Func6==`OUTHX || m1Func6==`OUTCX || m1Func6==`OUTBX
|
|
))
|
|
;
|
|
|
wire m2IsInW = m2Opcode==`INW;
|
wire m2IsInW = m2Opcode==`INW;
|
wire xIsIO = xIsIn || xIsOut;
|
wire xIsIO = xIsIn || xIsOut;
|
|
wire m1IsIO = m1IsIn || m1IsOut;
|
|
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFP = xOpcode==`FP;
|
wire xIsFP = xOpcode==`FP;
|
wire xneedBus = xIsIO;
|
wire xneedBus = xIsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
| Line 1281... |
Line 1320... |
m1IsLoad <= 1'b0;
|
m1IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m1IsStore <= 1'b0;
|
m1IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
m1IsIO <= 1'b0;
|
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
prev_ihit <= 1'b0;
|
prev_ihit <= 1'b0;
|
dhwxtype <= 2'b00;
|
|
xhwxtype <= 2'b00;
|
|
m1hwxtype <= 2'b00;
|
|
m2hwxtype <= 2'b00;
|
|
whwxtype <= 2'b00;
|
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
| Line 1304... |
Line 1337... |
m2pcv <= 1'b0;
|
m2pcv <= 1'b0;
|
wpcv <= 1'b0;
|
wpcv <= 1'b0;
|
tick <= 64'd0;
|
tick <= 64'd0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
dAXC <= 4'd0;
|
dAXC <= 4'd0;
|
|
xAXC <= 4'd0;
|
|
m1AXC <= 4'd0;
|
|
m2AXC <= 4'd0;
|
|
wAXC <= 4'd0;
|
xirqf <= 1'b0;
|
xirqf <= 1'b0;
|
dextype <= 9'h00;
|
dextype <= 9'h00;
|
xextype <= 9'h00;
|
xextype <= 9'h00;
|
m1extype <= 9'h00;
|
m1extype <= 9'h00;
|
m2extype <= 9'h00;
|
m2extype <= 9'h00;
|
| Line 1397... |
Line 1434... |
$display("*****************");
|
$display("*****************");
|
$display("NMI edge detected");
|
$display("NMI edge detected");
|
$display("*****************");
|
$display("*****************");
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
dhwxtype <= 2'b01;
|
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
end
|
end
|
else if (irq_i & !im & !StatusHWI) begin
|
else if (irq_i & !im & !StatusHWI) begin
|
| Line 1409... |
Line 1445... |
$display("IRQ detected");
|
$display("IRQ detected");
|
$display("*****************");
|
$display("*****************");
|
bu_im <= 1'b0;
|
bu_im <= 1'b0;
|
im <= 1'b1;
|
im <= 1'b1;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dhwxtype <= 2'b10;
|
|
dextype <= `EX_IRQ;
|
dextype <= `EX_IRQ;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
end
|
end
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// Are we filling the pipeline with NOP's as a result of a previous
|
// hardware interrupt ?
|
// hardware interrupt ?
|
else if (|dhwxtype|dFip|LoadNOPs)
|
else if (|dFip|LoadNOPs)
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
`ifdef TLB
|
`ifdef TLB
|
else if (ITLBMiss)
|
else if (ITLBMiss)
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
`endif
|
`endif
|
| Line 1442... |
Line 1477... |
begin
|
begin
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
// if (!LoadNOPs)
|
// if (!LoadNOPs)
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
case(iOpcode)
|
case(iOpcode)
|
`MISC:
|
|
case(iFunc)
|
|
`FIP: dFip <= 1'b1;
|
|
default: ;
|
|
endcase
|
|
// We predict the return address by storing it in a return address stack
|
// We predict the return address by storing it in a return address stack
|
// during a call instruction, then popping it off the stack in a return
|
// during a call instruction, then popping it off the stack in a return
|
// instruction. The prediction will not always be correct, if it's wrong
|
// instruction. The prediction will not always be correct, if it's wrong
|
// it's corrected by the EX stage branching to the right address.
|
// it's corrected by the EX stage branching to the right address.
|
`CALL:
|
`CALL:
|
| Line 1528... |
Line 1558... |
// - x???? signals to EX stage
|
// - x???? signals to EX stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//
|
//
|
if (advanceR) begin
|
if (advanceR) begin
|
xAXC <= dAXC;
|
xAXC <= dAXC;
|
xhwxtype <= dhwxtype;
|
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
xpc <= dpc;
|
xpc <= dpc;
|
xpcv <= dpcv;
|
xpcv <= dpcv;
|
xbranch_taken <= dbranch_taken;
|
xbranch_taken <= dbranch_taken;
|
| Line 1551... |
Line 1580... |
`BTRI: imm <= {{53{dIR[10]}},dIR[10:0]};
|
`BTRI: imm <= {{53{dIR[10]}},dIR[10:0]};
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
imm <= {{56{dIR[7]}},dIR[7:0]};
|
imm <= {{56{dIR[7]}},dIR[7:0]};
|
`RET: imm <= {49'h00000000,dIR[14:3],3'b000};
|
`RET: imm <= {49'h00000000,dIR[14:3],3'b000};
|
`MEMNDX: imm <= dIR[7:6];
|
`MEMNDX: imm <= dIR[7:6];
|
|
`STBC: imm <= {{52{dIR[11]}},dIR[11:0]};
|
default: imm <= {{49{dIR[14]}},dIR[14:0]};
|
default: imm <= {{49{dIR[14]}},dIR[14:0]};
|
endcase
|
endcase
|
scale <= dIR[9:8];
|
scale <= dIR[9:8];
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceX) begin
|
else if (advanceX) begin
|
xRtZero <= 1'b1;
|
xRtZero <= #1 1'b1;
|
xextype <= `EX_NON;
|
xextype <= #1 `EX_NON;
|
xbranch_taken <= 1'b0;
|
xbranch_taken <= #1 1'b0;
|
xIR <= `NOP_INSN;
|
xIR <= #1 `NOP_INSN;
|
xpcv <= 1'b0;
|
xpcv <= #1 1'b0;
|
xpc <= `RESET_VECTOR;
|
xpc <= #1 `RESET_VECTOR;
|
|
xFip <= #1 1'b0;
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// EXECUTE:
|
// EXECUTE:
|
// - perform datapath operation
|
// - perform datapath operation
|
// - perform virtual to physical address translation.
|
// - perform virtual to physical address translation.
|
// Outputs:
|
// Outputs:
|
// - m1???? signals to M1 stage
|
// - m1???? signals to M1 stage
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
m1hwxtype <= xhwxtype;
|
|
m1extype <= xextype;
|
m1extype <= xextype;
|
m1Fip <= xFip;
|
m1Fip <= xFip;
|
m1Func <= xFunc;
|
m1Func <= xFunc;
|
m1pcv <= xpcv;
|
m1pcv <= xpcv;
|
m1pc <= xpc;
|
m1pc <= xpc;
|
m1IR <= xIR;
|
m1IR <= xIR;
|
m1IsLoad <= xIsLoad;
|
m1IsLoad <= xIsLoad;
|
m1IsStore <= xIsStore;
|
m1IsStore <= xIsStore;
|
m1IsCnt <= xIsCnt;
|
m1IsCnt <= xIsCnt;
|
m1IsIO <= xIsIO;
|
|
m1Opcode <= xOpcode;
|
m1Opcode <= xOpcode;
|
m1Rt <= xRtZero ? 9'd0 : xRt;
|
m1Rt <= xRtZero ? 9'd0 : xRt;
|
m1Data <= xData;
|
m1Data <= xData;
|
m1IsCacheElement <= xisCacheElement;
|
m1IsCacheElement <= xisCacheElement;
|
m1AXC <= xAXC;
|
m1AXC <= xAXC;
|
| Line 1619... |
Line 1648... |
`WAIT: m1clkoff <= 1'b1;
|
`WAIT: m1clkoff <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`DCACHE_ON: dcache_on <= 1'b1;
|
`DCACHE_ON: dcache_on <= 1'b1;
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`IEPP: eptr <= eptr + 8'd1;
|
`FIP: begin
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
xRtZero <= 1'b1;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
dFip <= 1'b1;
|
|
xFip <= 1'b1;
|
|
m1Fip <= 1'b1;
|
|
end
|
|
`IEPP: begin
|
|
eptr <= eptr + 8'd1;
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
xRtZero <= 1'b1;
|
|
xpcv <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
dFip <= 1'b1;
|
|
xFip <= 1'b1;
|
|
m1Fip <= 1'b1;
|
|
end
|
`GRAN: begin
|
`GRAN: begin
|
rando <= rand;
|
rando <= rand;
|
m_z <= next_m_z;
|
m_z <= next_m_z;
|
m_w <= next_m_w;
|
m_w <= next_m_w;
|
end
|
end
|
| Line 1634... |
Line 1683... |
end
|
end
|
`IRET:
|
`IRET:
|
if (StatusHWI) begin
|
if (StatusHWI) begin
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
im <= 1'b0;
|
im <= 1'b0;
|
pc <= a;
|
pc <= IPC[xAXC]; //a;
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xRtZero <= 1'b1;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`ERET:
|
`ERET:
|
if (StatusEXL) begin
|
if (StatusEXL) begin
|
StatusEXL <= 1'b0;
|
StatusEXL <= 1'b0;
|
pc <= a;
|
pc <= EPC[xAXC];
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xRtZero <= 1'b1;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
| Line 1666... |
Line 1715... |
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xRtZero <= 1'b1;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
|
LoadNOPs <= 1'b1;
|
$display("EX SYSCALL thru %h",{TBA[63:12],xIR[15:7],3'b000});
|
$display("EX SYSCALL thru %h",{TBA[63:12],xIR[15:7],3'b000});
|
end
|
end
|
`ifdef TLB
|
`ifdef TLB
|
`TLBP: ea <= TLBVirtPage;
|
`TLBP: ea <= TLBVirtPage;
|
`endif
|
`endif
|
| Line 1685... |
Line 1735... |
xRtZero <= 1'b1;
|
xRtZero <= 1'b1;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
end
|
end
|
`MTSPR:
|
`MTSPR:
|
case(xIR[12:7])
|
case(xIR[11:6])
|
`ifdef TLB
|
`ifdef TLB
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`PageTableAddr: PageTableAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`BadVAddr: BadVAddr <= a[63:13];
|
`endif
|
`endif
|
`ASID: ASID <= a[7:0];
|
`ASID: ASID <= a[7:0];
|
`EPC: EPC <= a;
|
// `EPC: EPC <= a;
|
`TBA: TBA <= {a[63:12],12'h000};
|
`TBA: TBA <= {a[63:12],12'h000};
|
// `AXC: AXC <= a[3:0];
|
// `AXC: AXC <= a[3:0];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`NON_ICACHE_SEG: nonICacheSeg <= a[63:32];
|
`FPCR: rm <= a[31:30];
|
`FPCR: rm <= a[31:30];
|
`IPC: IPC <= a;
|
// `IPC: IPC <= a;
|
`SRAND1: begin
|
`SRAND1: begin
|
m_z <= a;
|
m_z <= a;
|
end
|
end
|
`SRAND2: begin
|
`SRAND2: begin
|
m_w <= a;
|
m_w <= a;
|
| Line 1721... |
Line 1771... |
default: ;
|
default: ;
|
endcase
|
endcase
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// JMP and CALL change the program counter immediately in the IF stage.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
// There's no work to do here. The pipeline does not need to be cleared.
|
`JMP: ;
|
`JMP: ;
|
`CALL: m1Data <= fnIncPC(xpc);
|
`CALL: ;//m1Data <= fnIncPC(xpc);
|
|
|
`JAL:
|
`JAL:
|
`ifdef BTB
|
`ifdef BTB
|
if (dpc[63:2] != a[63:2] + imm[63:2]) begin
|
if (dpc[63:2] != a[63:2] + imm[63:2]) begin
|
pc[63:2] <= a[63:2] + imm[63:2];
|
pc[63:2] <= a[63:2] + imm[63:2];
|
| Line 1862... |
Line 1912... |
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xRtZero <= 1'b1;
|
xpcv <= 1'b0;
|
xpcv <= 1'b0;
|
dpcv <= 1'b0;
|
dpcv <= 1'b0;
|
|
LoadNOPs <= 1'b1;
|
end
|
end
|
|
|
`INW:
|
`INW:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
| Line 1904... |
Line 1955... |
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData;
|
adr_o <= xData1;
|
end
|
end
|
`OUTW:
|
`OUTW:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
| Line 1967... |
Line 2018... |
begin
|
begin
|
m1Data <= b;
|
m1Data <= b;
|
ea <= xData1;
|
ea <= xData1;
|
$display("EX MEMOP %h", xData1);
|
$display("EX MEMOP %h", xData1);
|
end
|
end
|
|
// `STBC:
|
|
// begin
|
|
// m1Data <= {8{xIR[19:12]}};
|
|
// ea <= xData1;
|
|
// end
|
`SSH: begin
|
`SSH: begin
|
case(xRt)
|
case(xRt)
|
`SR: m1Data <= {2{sr}};
|
`SR: m1Data <= {2{sr}};
|
default: m1Data <= 64'd0;
|
default: m1Data <= 64'd0;
|
endcase
|
endcase
|
| Line 2177... |
Line 2233... |
end
|
end
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceM1) begin
|
else if (advanceM1) begin
|
m1IR <= `NOP_INSN;
|
m1IR <= #1 `NOP_INSN;
|
m1Opcode <= `NOPI;
|
m1Opcode <= #1 `NOPI;
|
m1Rt <= 9'd0;
|
m1Rt <= #1 9'd0;
|
m1clkoff <= 1'b0;
|
m1clkoff <= #1 1'b0;
|
m1pc <= `RESET_VECTOR;
|
m1Fip <= #1 1'b0;
|
m1pcv <= 1'b0;
|
m1pc <= #1 `RESET_VECTOR;
|
m1extype <= `EX_NON;
|
m1pcv <= #1 1'b0;
|
|
m1extype <= #1 `EX_NON;
|
m1IsLoad <= #1 1'b0;
|
m1IsLoad <= #1 1'b0;
|
m1IsStore <= #1 1'b0;
|
m1IsStore <= #1 1'b0;
|
m1IsCnt <= #1 1'b0;
|
m1IsCnt <= #1 1'b0;
|
m1IsIO <= #1 1'b0;
|
|
m1IsCacheElement <= #1 1'b0;
|
m1IsCacheElement <= #1 1'b0;
|
end
|
end
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 2209... |
Line 2265... |
// Outputs:
|
// Outputs:
|
// - m2???? signals to M2 stage
|
// - m2???? signals to M2 stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
if (advanceM1) begin
|
if (advanceM1) begin
|
m2extype <= m1extype;
|
m2extype <= m1extype;
|
m2hwxtype <= m1hwxtype;
|
|
m2Addr <= pea;
|
m2Addr <= pea;
|
m2Data <= m1Data;
|
m2Data <= m1Data;
|
m2Fip <= m1Fip;
|
m2Fip <= m1Fip;
|
m2pc <= m1pc;
|
m2pc <= m1pc;
|
m2pcv <= m1pcv;
|
m2pcv <= m1pcv;
|
m2IR <= m1IR;
|
m2IR <= m1IR;
|
m2Opcode <= m1Opcode;
|
m2Opcode <= m1Opcode;
|
m2Func <= m1Func;
|
m2Func <= m1Func;
|
m2IsLoad <= m1IsLoad;
|
m2IsLoad <= #1 m1IsLoad;
|
m2IsStore <= #1 m1IsStore;
|
m2IsStore <= #1 m1IsStore;
|
m2IsCnt <= m1IsCnt;
|
m2IsCnt <= m1IsCnt;
|
m2Func <= m1Func;
|
m2Func <= m1Func;
|
m2Rt <= m1Rt;
|
m2Rt <= m1Rt;
|
m2clkoff <= m1clkoff;
|
m2clkoff <= m1clkoff;
|
| Line 2670... |
Line 2725... |
m2IsCnt <= #1 1'b0;
|
m2IsCnt <= #1 1'b0;
|
m2Func <= #1 7'd0;
|
m2Func <= #1 7'd0;
|
m2Addr <= 64'd0;
|
m2Addr <= 64'd0;
|
m2Data <= #1 64'd0;
|
m2Data <= #1 64'd0;
|
m2clkoff <= #1 1'b0;
|
m2clkoff <= #1 1'b0;
|
|
m2Fip <= #1 1'b0;
|
m2pcv <= #1 1'b0;
|
m2pcv <= #1 1'b0;
|
m2pc <= #1 `RESET_VECTOR;
|
m2pc <= #1 `RESET_VECTOR;
|
m2extype <= #1 `EX_NON;
|
m2extype <= #1 `EX_NON;
|
end
|
end
|
|
|
| Line 2687... |
Line 2743... |
// Outputs:
|
// Outputs:
|
// - w???? signals to WB stage
|
// - w???? signals to WB stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
if (advanceM2) begin
|
if (advanceM2) begin
|
wextype <= #1 m2extype;
|
wextype <= #1 m2extype;
|
whwxtype <= #1 m2hwxtype;
|
|
wpc <= #1 m2pc;
|
wpc <= #1 m2pc;
|
wpcv <= #1 m2pcv;
|
wpcv <= #1 m2pcv;
|
wFip <= #1 m2Fip;
|
wFip <= #1 m2Fip;
|
wIsStore <= #1 m2IsStore;
|
wIsStore <= #1 m2IsStore;
|
wIR <= #1 m2IR;
|
wIR <= #1 m2IR;
|
wOpcode <= #1 m2Opcode;
|
wOpcode <= #1 m2Opcode;
|
wFunc <= #1 m2Func;
|
wFunc <= #1 m2Func;
|
wData <= #1 m2Data;
|
wData <= #1 m2Data;
|
wRt <= #1 m2Rt;
|
wRt <= #1 m2Rt;
|
wclkoff <= #1 m2clkoff;
|
wclkoff <= #1 m2clkoff;
|
|
wAXC <= #1 m2AXC;
|
|
|
// There's not an error is a prefetch is taking place (m2Rt=0).
|
// There's not an error is a prefetch is taking place (m2Rt=0).
|
if (((m2IsLoad&&m2Rt[4:0]!=5'd0)|m2IsStore)&err_i) begin
|
if (((m2IsLoad&&m2Rt[4:0]!=5'd0)|m2IsStore)&err_i) begin
|
wextype <= #1 `EX_DBERR;
|
wextype <= #1 `EX_DBERR;
|
errorAddress <= #1 adr_o;
|
errorAddress <= #1 adr_o;
|
| Line 2822... |
Line 2878... |
wData <= 64'd0;
|
wData <= 64'd0;
|
wIR <= `NOP_INSN;
|
wIR <= `NOP_INSN;
|
wOpcode <= `NOPI;
|
wOpcode <= `NOPI;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
wclkoff <= 1'b0;
|
wclkoff <= 1'b0;
|
|
wFip <= 1'b0;
|
wpcv <= 1'b0;
|
wpcv <= 1'b0;
|
wpc <= `RESET_VECTOR;
|
wpc <= `RESET_VECTOR;
|
end
|
end
|
|
|
|
|
| Line 2854... |
Line 2911... |
im <= wData[15];
|
im <= wData[15];
|
FXE <= wData[12];
|
FXE <= wData[12];
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
`MISC:
|
|
case(wFunc)
|
|
`SYSCALL:
|
|
begin
|
|
if (wIR[24:20]==5'd25)
|
|
IPC[wAXC] <= wData;
|
|
else
|
|
EPC[wAXC] <= wData;
|
|
end
|
|
endcase
|
|
`R:
|
|
case(wIR[5:0])
|
|
`MTSPR:
|
|
case(wIR[11:6])
|
|
`IPC: IPC[wAXC] <= wData;
|
|
`EPC: EPC[wAXC] <= wData;
|
|
endcase
|
|
endcase
|
endcase
|
endcase
|
if (wclkoff)
|
if (wclkoff)
|
clk_en <= 1'b0;
|
clk_en <= 1'b0;
|
else
|
else
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
if (|whwxtype) begin
|
// FIP/IEPP:
|
dhwxtype <= 2'b00;
|
// Jump back to the instruction following the FIP/IEPP
|
xhwxtype <= 2'b00;
|
|
m1hwxtype <= 2'b00;
|
|
m2hwxtype <= 2'b00;
|
|
whwxtype <= 2'b00;
|
|
end
|
|
if (wFip) begin
|
if (wFip) begin
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
|
pc <= fnIncPC(wpc);
|
end
|
end
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// WRITEBACK (WB') - part two:
|
// WRITEBACK (WB') - part two:
|
// - vector to exception handler address
|
// - vector to exception handler address
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
| Line 2948... |
Line 3019... |
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
bl_o <= 5'd7;
|
bl_o <= 5'd7;
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
|
sel_o <= 8'hFF;
|
adr_o <= {pea[63:6],6'h00};
|
adr_o <= {pea[63:6],6'h00};
|
cstate <= DCACT;
|
cstate <= DCACT;
|
end
|
end
|
else if (triggerICacheLoad) begin
|
else if (triggerICacheLoad) begin
|
icaccess <= 1'b1;
|
icaccess <= 1'b1;
|
bte_o <= 2'b00; // linear burst
|
bte_o <= 2'b00; // linear burst
|
cti_o <= 3'b010; // burst access
|
cti_o <= 3'b010; // burst access
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
|
sel_o <= 8'hFF;
|
if (ICacheAct) begin
|
if (ICacheAct) begin
|
bl_o <= 5'd7;
|
bl_o <= 5'd7;
|
adr_o <= {ppc[63:6],6'h00};
|
adr_o <= {ppc[63:6],6'h00};
|
cstate <= ICACT1;
|
cstate <= ICACT1;
|
end
|
end
|
| Line 2979... |
Line 3052... |
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
else if (adr_o[5:3]==3'd7) begin
|
else if (adr_o[5:3]==3'd7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
|
sel_o <= 8'h00;
|
tmem[adr_o[12:6]] <= {1'b1,adr_o[63:13]}; // This will cause ihit to go high
|
tmem[adr_o[12:6]] <= {1'b1,adr_o[63:13]}; // This will cause ihit to go high
|
tvalid[adr_o[12:6]] <= 1'b1;
|
tvalid[adr_o[12:6]] <= 1'b1;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
| Line 3005... |
Line 3079... |
ibuftag1 <= adr_o[63:4];
|
ibuftag1 <= adr_o[63:4];
|
end
|
end
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
|
sel_o <= 8'h00;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
| Line 3019... |
Line 3094... |
cti_o <= 3'b111; // Last cycle ahead
|
cti_o <= 3'b111; // Last cycle ahead
|
if (adr_o[5:3]==3'h7) begin
|
if (adr_o[5:3]==3'h7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
|
sel_o <= 8'h00;
|
dcaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
|
|
