| Line 28... |
Line 28... |
//
|
//
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//`define ADDRESS_RESERVATION 1
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//`define ADDRESS_RESERVATION 1
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//`define FLOATING_POINT 1
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//`define FLOATING_POINT 1
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//`define BTB 1
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//`define BTB 1
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//`define TLB 1
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//`define TLB 1
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//`define SIMD 1
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`define SEGMENTATION 1
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|
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`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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`define RESET_VECTOR 64'hFFFF_FFFF_FFFF_FFF0
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|
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`define ITLB_MissHandler 64'hFFFF_FFFF_FFFF_FFC0
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`define DTLB_MissHandler 64'hFFFF_FFFF_FFFF_FFB0
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|
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`define EX_NON 9'd000
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`define EX_NON 9'd000
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`define EX_TRAP 9'd32 // Trap exception
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`define EX_TRAP 9'd32 // Trap exception
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`define EX_IRQ 9'd449 // interrupt
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`define EX_IRQ 9'd448 // base IRQ interrupt
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`define EX_DBZ 9'd488 // divide by zero
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`define EX_DBZ 9'd488 // divide by zero
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`define EX_OFL 9'd489 // overflow
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`define EX_OFL 9'd489 // overflow
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`define EX_UNIMP_INSN 9'd495 // unimplemented instruction
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`define EX_UNIMP_INSN 9'd495 // unimplemented instruction
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`define EX_PRIV 9'd496 // priviledge violation
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`define EX_PRIV 9'd496 // priviledge violation
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`define EX_TLBD 9'd506 // TLB exception - data
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`define EX_TLBD 9'd506 // TLB exception - data
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| Line 50... |
Line 49... |
`define EX_NMI 9'd510 // non-maskable interrupt
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`define EX_NMI 9'd510 // non-maskable interrupt
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`define EX_RST 9'd511 // Reset
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`define EX_RST 9'd511 // Reset
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|
|
`include "Raptor64_opcodes.v"
|
`include "Raptor64_opcodes.v"
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|
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, bte_o, cti_o, bl_o, iocyc_o,
|
module Raptor64sc(rst_i, clk_i, nmi_i, irq_i, irq_no, bte_o, cti_o, bl_o, iocyc_o,
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
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cyc_o, stb_o, ack_i, err_i, we_o, sel_o, rsv_o, adr_o, dat_i, dat_o, sys_adv, sys_adr
|
);
|
);
|
parameter IDLE = 5'd1;
|
parameter IDLE = 5'd1;
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parameter ICACT = 5'd2;
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parameter ICACT = 5'd2;
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parameter ICACT1 = 5'd4;
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parameter ICACT1 = 5'd4;
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| Line 66... |
Line 65... |
parameter RUN = 4'd1;
|
parameter RUN = 4'd1;
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input nmi_i;
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input nmi_i;
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input irq_i;
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input irq_i;
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input [4:0] irq_no;
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|
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output [1:0] bte_o; // burst type
|
output [1:0] bte_o; // burst type
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reg [1:0] bte_o;
|
reg [1:0] bte_o;
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output [2:0] cti_o; // cycle type
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output [2:0] cti_o; // cycle type
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reg [2:0] cti_o;
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reg [2:0] cti_o;
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| Line 99... |
Line 99... |
input [63:5] sys_adr;
|
input [63:5] sys_adr;
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|
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reg [3:0] state;
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reg [3:0] state;
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reg [5:0] fltctr;
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reg [5:0] fltctr;
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wire fltdone = fltctr==6'd0;
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wire fltdone = fltctr==6'd0;
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reg resetA;
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reg bu_im; // interrupt mask
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reg im,bu_im; // interrupt mask
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reg im1; // temporary interrupt mask for LM/SM
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reg im1; // temporary interrupt mask for LM/SM
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reg [7:0] ie_fuse; // interrupt enable fuse
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wire im = ~ie_fuse[7];
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reg [1:0] rm; // fp rounding mode
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reg [1:0] rm; // fp rounding mode
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reg FXE; // fp exception enable
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reg FXE; // fp exception enable
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wire KernelMode;
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wire KernelMode;
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wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,2'b00,10'b0};
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wire [31:0] sr = {bu_im,15'd0,im,1'b0,KernelMode,FXE,2'b00,10'b0};
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reg [31:0] dIR,xIR,m1IR,m2IR,wIR;
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reg [31:0] dIR,d1IR,xIR,m1IR,m2IR,wIR;
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reg [31:0] ndIR; // next dIR
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reg [31:0] ndIR; // next dIR
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reg [63:0] pc; // ipc
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reg [63:0] pc; // ipc
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wire [63:0] pchistoric;
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wire [63:0] pchistoric;
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reg pccap;
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reg pccap; // flag 1=capture PC history
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reg [63:0] ErrorEPC;
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reg [63:0] ErrorEPC;
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reg [63:0] EPC [0:15];
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reg [63:0] EPC [0:15]; // Exception return address
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reg [63:0] IPC [0:15];
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reg [63:0] IPC [0:15]; // Interrupt return address
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reg [63:0] PCS [0:15];
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`ifdef SEGMENTATION
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reg [15:0] StatusEXL;
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reg [63:16] CS [0:15]; // Code segment
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reg [63:0] dpc,xpc,m1pc,m2pc,wpc;
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reg [63:16] DS [0:15]; // Data segment
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reg ipcv,dpcv,xpcv,m1pcv,m2pcv,wpcv; // PC valid indicators
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reg [63:16] SS [0:15]; // Stack segment
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wire [63:0] rfoa,rfob,rfoc;
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reg [63:16] ES [0:15]; // BSS segment
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`endif
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reg dStatusHWI,xStatusHWI,m1StatusHWI,m2StatusHWI;
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reg dIm,xIm,m1Im,m2Im;
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reg dNmi,xNmi,m1Nmi,m2Nmi,wNmi;
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|
reg [15:0] StatusEXL; // 1= context in exception state
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reg [63:0] dpc,d1pc,xpc,m1pc,m2pc,wpc; // PC's associated with instruction in pipeline
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wire [63:0] rfoa,rfob,rfoc; // register file outputs
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wire [8:0] dRa,dRb,dRc;
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wire [8:0] dRa,dRb,dRc;
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reg [8:0] wRt,m1Rt,m2Rt,tRt;
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reg [8:0] xRt,wRt,m1Rt,m2Rt,tRt; // target register
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wire [8:0] xRt;
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reg [63:0] ea; // effective data address
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reg xRtZero;
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reg [4:0] cstate; // cache state
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reg [63:0] ea;
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reg dbranch_taken,xbranch_taken; // flag: 1=branch taken
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reg [4:0] cstate;
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reg dbranch_taken,xbranch_taken;
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reg [63:0] mutex_gate;
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reg [63:0] mutex_gate;
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reg [63:0] TBA; // Trap Base Address
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reg [63:0] TBA; // Trap Base Address
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reg [8:0] dextype,xextype,m1extype,m2extype,wextype,textype;
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reg [8:0] dextype,d1extype,xextype,m1extype,m2extype,wextype,textype;
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reg [3:0] epat [0:255];
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reg [3:0] epat [0:255];
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reg [7:0] eptr;
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reg [7:0] eptr;
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reg [3:0] dAXC,xAXC,m1AXC,m2AXC,wAXC;
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reg [3:0] dAXC,d1AXC,xAXC,m1AXC,m2AXC,wAXC; // context active per pipeline stage
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wire [3:0] AXC = (eptr==8'h00) ? 4'h0 : epat[eptr];
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wire [3:0] AXC = (eptr==8'h00) ? 4'h0 : epat[eptr];
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reg dtinit;
|
reg dtinit; // 1=data cache tags are being intialized
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reg dcache_on;
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reg dcache_on; // 1= data cache is enabled
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|
wire [63:0] cdat; // data cache output
|
reg [63:32] nonICacheSeg;
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reg [63:32] nonICacheSeg;
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reg [1:0] FPC_rm;
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reg [1:0] FPC_rm; // fp: rounding mode
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reg FPC_SL; // result is negative (and non-zero)
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reg FPC_SL; // result is negative (and non-zero)
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reg FPC_SE; // result is zero
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reg FPC_SE; // result is zero
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reg FPC_SG; // result is positive (and non-zero)
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reg FPC_SG; // result is positive (and non-zero)
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reg FPC_SI; // result is infinite or NaN
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reg FPC_SI; // result is infinite or NaN
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reg FPC_overx;
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reg FPC_overx;
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| Line 153... |
Line 160... |
FPC_SG,
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FPC_SG,
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FPC_SE,
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FPC_SE,
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FPC_SI,
|
FPC_SI,
|
16'd0
|
16'd0
|
};
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};
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wire [63:0] cdat;
|
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reg [63:0] wr_addr;
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reg [63:0] wr_addr;
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reg [31:0] insn;
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reg [31:0] insn;
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reg clk_en;
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reg clk_en;
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reg cpu_clk_en;
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reg cpu_clk_en;
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reg StatusERL; // 1= in error processing
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reg StatusERL; // 1= in error processing
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| Line 170... |
Line 176... |
reg [63:13] PageTableAddr;
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reg [63:13] PageTableAddr;
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reg [63:0] errorAddress;
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reg [63:0] errorAddress;
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|
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] iOpcode = insn[31:25];
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wire [6:0] iFunc = insn[6:0];
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wire [6:0] iFunc = insn[6:0];
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wire [5:0] iFunc6 = insn[5:0];
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wire [6:0] dOpcode = dIR[31:25];
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wire [6:0] dOpcode = dIR[31:25];
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wire [6:0] dFunc = dIR[6:0];
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wire [6:0] dFunc = dIR[6:0];
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wire [5:0] dFunc6 = dIR[5:0];
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wire [5:0] dFunc6 = dIR[5:0];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xOpcode = xIR[31:25];
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wire [6:0] xFunc = xIR[6:0];
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wire [6:0] xFunc = xIR[6:0];
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wire [5:0] xFunc6 = xIR[5:0];
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wire [5:0] xFunc6 = xIR[5:0];
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wire [4:0] xFunc5 = xIR[4:0];
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wire [4:0] xFunc5 = xIR[4:0];
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reg [6:0] m1Opcode,m2Opcode,wOpcode;
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wire [6:0] m1Opcode,m2Opcode,wOpcode;
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reg [6:0] m1Func,m2Func,wFunc;
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assign m1Opcode = m1IR[31:25];
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assign m2Opcode = m2IR[31:25];
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assign wOpcode = wIR[31:25];
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wire [6:0] m1Func,m2Func,wFunc;
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assign m1Func = m1IR[6:0];
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assign m2Func = m2IR[6:0];
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assign wFunc = wIR[6:0];
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wire [5:0] m1Func6 = m1Func[5:0];
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wire [5:0] m1Func6 = m1Func[5:0];
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wire [5:0] m2Func6 = m2Func[5:0];
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wire [5:0] m2Func6 = m2Func[5:0];
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wire [5:0] wFunc6 = wIR[5:0];
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wire [5:0] wFunc6 = wIR[5:0];
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reg [63:0] m1Data,m2Data,wData,tData;
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reg [63:0] m1Data,m2Data,wData,tData;
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reg [63:0] m2Addr;
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reg [63:0] m2Addr;
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reg [63:0] tick;
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reg [63:0] tick;
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reg [63:0] a,b,c,imm,m1b;
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reg [63:0] a,b,c,imm,m1b;
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reg [1:0] scale;
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wire [1:0] scale = xIR[9:8];
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reg prev_ihit;
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wire [1:0] offset2 = xIR[7:6];
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reg rsf;
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reg rsf; // reserrved address flag
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reg [63:5] resv_address;
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reg [63:5] resv_address; // reserved address
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reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
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reg dirqf,rirqf,m1irqf,m2irqf,wirqf,tirqf;
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reg xirqf;
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reg xirqf;
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wire advanceX_edge;
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wire advanceX_edge;
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wire takb;
|
wire takb;
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wire advanceI,advanceR,advanceX,advanceM1,advanceW,advanceT;
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wire advanceI,advanceR,advanceR1,advanceX,advanceM1,advanceW,advanceT; // Pipeline advance signals
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reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
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reg m1clkoff,m2clkoff,m3clkoff,m4clkoff,wclkoff;
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reg dFip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg dFip,d1Fip,xFip,m1Fip,m2Fip,m3Fip,m4Fip,wFip;
|
reg cyc1;
|
reg cyc1;
|
reg LoadNOPs;
|
reg LoadNOPs;
|
reg dIRvalid,xIRvalid,m1IRvalid,m2IRvalid,wIRvalid,tIRvalid;
|
reg m1IsLoad,m1IsStore;
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reg m2IsLoad,m2IsStore;
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reg wIsStore;
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reg m1IsOut,m1IsIn;
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|
|
function [63:0] fnIncPC;
|
function [63:0] fnIncPC;
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input [63:0] fpc;
|
input [63:0] fpc;
|
begin
|
begin
|
fnIncPC = fpc + 64'd4;
|
fnIncPC = fpc + 64'd4;
|
end
|
end
|
endfunction
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endfunction
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|
|
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function [7:0] fnSelect;
|
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input [6:0] opcode;
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|
input [2:0] addr;
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case(opcode)
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`LBU,`LB,`SB,`INB,`INBU,`OUTB:
|
|
case(addr)
|
|
3'b000: fnSelect = 8'b00000001;
|
|
3'b001: fnSelect = 8'b00000010;
|
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3'b010: fnSelect = 8'b00000100;
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3'b011: fnSelect = 8'b00001000;
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3'b100: fnSelect = 8'b00010000;
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3'b101: fnSelect = 8'b00100000;
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3'b110: fnSelect = 8'b01000000;
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3'b111: fnSelect = 8'b10000000;
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|
endcase
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`LC,`LCU,`SC,`INCH,`INCU,`OUTC:
|
|
case(addr[2:1])
|
|
2'b00: fnSelect = 8'b00000011;
|
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2'b01: fnSelect = 8'b00001100;
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2'b10: fnSelect = 8'b00110000;
|
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2'b11: fnSelect = 8'b11000000;
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endcase
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`LHU,`LH,`SH,`LSH,`LF,`LFP,`SF,`SFP,`SSH,`INH,`INHU,`OUTH:
|
|
case(addr[2])
|
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1'b0: fnSelect = 8'b00001111;
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1'b1: fnSelect = 8'b11110000;
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endcase
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`LW,`LWR,`LM,`LFD,`LSW,`LP,`LFDP,
|
|
`SW,`SM,`SFD,`SSW,`SWC,`SP,`SFDP,`INW,`OUTW:
|
|
fnSelect = 8'b11111111;
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endcase
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endfunction
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|
|
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reg [7:0] data8;
|
|
reg [15:0] data16;
|
|
reg [31:0] data32;
|
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reg [63:0] data64;
|
|
|
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always @(sel_o or dat_i)
|
|
case(sel_o)
|
|
8'b00000001: data8 <= #1 dat_i[ 7: 0];
|
|
8'b00000010: data8 <= #1 dat_i[15: 8];
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8'b00000100: data8 <= #1 dat_i[23:16];
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8'b00001000: data8 <= #1 dat_i[31:24];
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8'b00010000: data8 <= #1 dat_i[39:32];
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8'b00100000: data8 <= #1 dat_i[47:40];
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8'b01000000: data8 <= #1 dat_i[55:48];
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8'b10000000: data8 <= #1 dat_i[63:56];
|
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default: data8 <= 8'h00;
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endcase
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|
|
|
always @(sel_o or dat_i)
|
|
case(sel_o)
|
|
8'b00000011: data16 <= #1 dat_i[15: 0];
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8'b00001100: data16 <= #1 dat_i[31:16];
|
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8'b00110000: data16 <= #1 dat_i[47:32];
|
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8'b11000000: data16 <= #1 dat_i[63:48];
|
|
default: data16 <= #1 16'hDEAD;
|
|
endcase
|
|
|
|
always @(sel_o or dat_i)
|
|
case(sel_o)
|
|
8'b00001111: data32 <= #1 dat_i[31: 0];
|
|
8'b11110000: data32 <= #1 dat_i[63:32];
|
|
default: data32 <= #1 32'hDEADDEAD;
|
|
endcase
|
|
|
|
always @(sel_o or dat_i)
|
|
data64 <= #1 dat_i;
|
|
|
assign KernelMode = StatusEXL[xAXC]|StatusHWI;
|
assign KernelMode = StatusEXL[xAXC]|StatusHWI;
|
|
|
wire iIsLSPair = iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP;
|
//wire iIsLSPair = iOpcode==`SP || iOpcode==`LP || iOpcode==`SFP || iOpcode==`LFP || iOpcode==`SFDP || iOpcode==`LFDP ||
|
wire dIsLSPair = dOpcode==`SP || dOpcode==`LP || dOpcode==`SFP || dOpcode==`LFP || dOpcode==`SFDP || dOpcode==`LFDP;
|
// (iOpcode==`MEMNDX && (iFunc6==`SPX || iFunc6==`LPX || iFunc6==`SFPX || iFunc6==`LFPX || iFunc6==`SFDPX || iFunc6==`LFDPX));
|
|
//wire dIsLSPair = dOpcode==`SP || dOpcode==`LP || dOpcode==`SFP || dOpcode==`LFP || dOpcode==`SFDP || dOpcode==`LFDP ||
|
|
// (dOpcode==`MEMNDX && (dFunc6==`SPX || dFunc6==`LPX || dFunc6==`SFPX || dFunc6==`LFPX || dFunc6==`SFDPX || dFunc6==`LFDPX));
|
|
//wire xIsLSPair = xOpcode==`SP || xOpcode==`LP || xOpcode==`SFP || xOpcode==`LFP || xOpcode==`SFDP || xOpcode==`LFDP ||
|
|
// (xOpcode==`MEMNDX && (xFunc6==`SPX || xFunc6==`LPX || xFunc6==`SFPX || xFunc6==`LFPX || xFunc6==`SFDPX || xFunc6==`LFDPX));
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// Segmentation
|
|
//
|
|
// If the upper nybble of the address is 'F' then segmentation is not applied.
|
|
// This allows for bootstrapping and operating system use. Also when in kernel
|
|
// mode the lowest 64k of memory is unsegmented to allow easier access to
|
|
// operating system variables.
|
|
//
|
|
// Otherwise: the CS register is always in use for code addresses.
|
|
// Which segment is used for data addresses depends on the upper nybble of
|
|
// the address.
|
|
//-----------------------------------------------------------------------------
|
|
`ifdef SEGMENTATION
|
|
wire [63:0] spc; // segmented PC
|
|
reg [63:0] sea; // segmented effective address
|
|
assign spc = pc[63:60]==4'hF ? pc : {CS[AXC][63:16] + pc[59:16],pc[15:0]};
|
|
always @(ea or KernelMode)
|
|
if (KernelMode && ea[63:16]==48'h0)
|
|
sea <= ea;
|
|
else
|
|
case(ea[63:60])
|
|
4'hF: sea <= ea;
|
|
4'hE: sea <= {SS[xAXC][63:16] + ea[59:16],ea[15:0]};
|
|
4'hD: sea <= {ES[xAXC][63:16] + ea[59:16],ea[15:0]};
|
|
default:
|
|
sea <= {DS[xAXC][63:16] + ea[59:16],ea[15:0]};
|
|
endcase
|
|
`else
|
|
wire [63:0] spc = pc;
|
|
wire [63:0] sea = ea;
|
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// TLB
|
// TLB
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB contains 64 entries, that are 8 way set associative.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
// The TLB is dual ported and shared between the instruction and data streams.
|
| Line 223... |
Line 346... |
wire [63:0] ppc;
|
wire [63:0] ppc;
|
wire [63:0] pea;
|
wire [63:0] pea;
|
wire [63:0] tlbo;
|
wire [63:0] tlbo;
|
`ifdef TLB
|
`ifdef TLB
|
wire [63:0] TLBVirtPage;
|
wire [63:0] TLBVirtPage;
|
wire wTlbp = wIRvalid && advanceW && wOpcode==`MISC && wFunc==`TLBP;
|
wire wTlbp = advanceW && wOpcode==`MISC && wFunc==`TLBP;
|
wire wTlbrd = wIRvalid && advanceW && wOpcode==`MISC && wFunc==`TLBR;
|
wire wTlbrd = advanceW && wOpcode==`MISC && wFunc==`TLBR;
|
wire wTlbwr = wIRvalid && advanceW && wOpcode==`MISC && wFunc==`TLBWR;
|
wire wTlbwr = advanceW && wOpcode==`MISC && wFunc==`TLBWR;
|
wire wTlbwi = wIRvalid && advanceW && wOpcode==`MISC && wFunc==`TLBWI;
|
wire wTlbwi = advanceW && wOpcode==`MISC && wFunc==`TLBWI;
|
wire wMtspr = wIRvalid && advanceW && wOpcode==`R && wFunc==`MTSPR;
|
wire wMtspr = advanceW && wOpcode==`R && wFunc==`MTSPR;
|
wire xTlbrd = xIRvalid && advanceX && xOpcode==`MISC && xFunc==`TLBR;
|
wire xTlbrd = advanceX && xOpcode==`MISC && xFunc==`TLBR;
|
wire xTlbwr = xIRvalid && advanceX && xOpcode==`MISC && xFunc==`TLBWR;
|
wire xTlbwr = advanceX && xOpcode==`MISC && xFunc==`TLBWR;
|
wire xTlbwi = xIRvalid && advanceX && xOpcode==`MISC && xFunc==`TLBWI;
|
wire xTlbwi = advanceX && xOpcode==`MISC && xFunc==`TLBWI;
|
wire ITLBMiss,DTLBMiss;
|
wire ITLBMiss,DTLBMiss;
|
|
|
Raptor64_TLB u22
|
Raptor64_TLB u26
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.pc(pc),
|
.pc(spc),
|
.ea(ea),
|
.ea(sea),
|
.ppc(ppc),
|
.ppc(ppc),
|
.pea(pea),
|
.pea(pea),
|
.m1IsStore(advanceM1 && m1IsStore),
|
.m1IsStore(advanceM1 && m1IsStore),
|
.ASID(ASID),
|
.ASID(ASID),
|
.wTlbp(wTlbp),
|
.wTlbp(wTlbp),
|
| Line 251... |
Line 374... |
.wTlbwi(wTlbwi),
|
.wTlbwi(wTlbwi),
|
.xTlbrd(xTlbrd),
|
.xTlbrd(xTlbrd),
|
.xTlbwr(xTlbwr),
|
.xTlbwr(xTlbwr),
|
.xTlbwi(xTlbwi),
|
.xTlbwi(xTlbwi),
|
.wr(wMtspr),
|
.wr(wMtspr),
|
.wregno(wIR[12:7]),
|
.wregno(wIR[11:6]),
|
.dati(wData),
|
.dati(wData),
|
.xregno(xIR[12:7]),
|
.xregno(xIR[11:6]),
|
.dato(tlbo),
|
.dato(tlbo),
|
.ITLBMiss(ITLBMiss),
|
.ITLBMiss(ITLBMiss),
|
.DTLBMiss(DTLBMiss),
|
.DTLBMiss(DTLBMiss),
|
.HTLBVirtPage(TLBVirtPage)
|
.HTLBVirtPage(TLBVirtPage)
|
);
|
);
|
|
|
`else
|
`else
|
assign ppc = pc;
|
assign ppc = spc;
|
assign pea = ea;
|
assign pea = sea;
|
`endif
|
`endif
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Clock control
|
// Clock control
|
// - reset or NMI reenables the clock
|
// - reset or NMI reenables the clock
|
| Line 283... |
Line 406... |
if (nmi_i)
|
if (nmi_i)
|
cpu_clk_en <= 1'b1;
|
cpu_clk_en <= 1'b1;
|
else
|
else
|
cpu_clk_en <= clk_en;
|
cpu_clk_en <= clk_en;
|
end
|
end
|
|
//assign clk = clk_i;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Random number register:
|
// Random number register:
|
//
|
//
|
// Uses George Marsaglia's multiply method.
|
// Uses George Marsaglia's multiply method.
|
| Line 315... |
Line 439... |
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Instruction Cache / Instruction buffer
|
// Instruction Cache / Instruction buffer
|
//
|
//
|
// On a bus error, the instruction cache / buffer is loaded with a SYSCALL 509
|
// On a bus error, the instruction cache / buffer is loaded with a SYSCALL 509
|
// instruction, which is a call to the bus error handler.
|
// instruction, which is a call to the bus error handler.
|
|
// Line size is 16 half-words (64 bytes). Total cache size is 16kB.
|
//
|
//
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//reg lfdir;
|
//reg lfdir;
|
reg icaccess;
|
reg icaccess;
|
reg ICacheOn;
|
reg ICacheOn;
|
| Line 332... |
Line 457... |
reg [31:0] insn1;
|
reg [31:0] insn1;
|
reg [31:0] insnkey;
|
reg [31:0] insnkey;
|
reg [63:0] icadr;
|
reg [63:0] icadr;
|
|
|
// SYSCALL 509
|
// SYSCALL 509
|
wire syscall509 = 32'b0000000_11000_0000_11111110_10010111;
|
wire syscall509 = 32'b0000000_00000_0000_11111110_10010111;
|
wire [63:0] bevect = {syscall509,syscall509};
|
wire [63:0] bevect = {syscall509,syscall509};
|
|
|
// Xilinx Core Generator Component
|
|
Raptor64_icache_ram u1
|
Raptor64_icache_ram u1
|
(
|
(
|
.clka(clk), // input clka
|
.wclk(clk),
|
.wea(icaccess & (ack_i|err_i)), // input [0 : 0] wea
|
.we(icaccess & (ack_i|err_i)),
|
.addra(icadr[12:3]), // input [9 : 0] addra
|
.adr(icadr[13:0]),
|
.dina(err_i ? bevect : dat_i), // input [63 : 0] dina
|
.d(err_i ? bevect : dat_i),
|
.clkb(~clk), // input clkb
|
.rclk(~clk),
|
.addrb(pc[12:2]), // input [8 : 0] addrb
|
.pc(pc[13:0]),
|
.doutb(insnbundle) // output [127 : 0] doutb
|
.insn(insnbundle)
|
);
|
);
|
|
|
always @(insnbundle or ICacheAct or insnbuf)
|
always @(insnbundle or ICacheAct or insnbuf)
|
begin
|
begin
|
case(ICacheAct)
|
case(ICacheAct)
|
| Line 359... |
Line 483... |
|
|
// Decrypt the instruction set.
|
// Decrypt the instruction set.
|
always @(insn1,insnkey)
|
always @(insn1,insnkey)
|
insn <= insn1 ^ insnkey;
|
insn <= insn1 ^ insnkey;
|
|
|
reg [63:13] tmem [127:0];
|
reg [63:14] tmem [255:0];
|
reg [127:0] tvalid;
|
reg [255:0] tvalid;
|
|
|
initial begin
|
initial begin
|
for (n=0; n < 128; n = n + 1)
|
for (n=0; n < 256; n = n + 1)
|
tmem[n] = 0;
|
tmem[n] = 0;
|
for (n=0; n < 128; n = n + 1)
|
for (n=0; n < 256; n = n + 1)
|
tvalid[n] = 0;
|
tvalid[n] = 0;
|
end
|
end
|
|
|
wire [64:13] tgout;
|
wire [64:14] tgout;
|
assign tgout = {tvalid[pc[12:6]],tmem[pc[12:6]]};
|
assign tgout = {tvalid[pc[13:6]],tmem[pc[13:6]]};
|
assign ihit = (tgout=={1'b1,ppc[63:13]});
|
assign ihit = (tgout=={1'b1,ppc[63:14]});
|
assign ibufrdy = ibufadr[63:2]==ppc[63:2];
|
assign ibufrdy = ibufadr[63:2]==ppc[63:2];
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Data Cache
|
// Data Cache
|
// No-allocate on write
|
// No-allocate on write
|
|
// Line size is 8 words (64 bytes). Total cache size is 32kB
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
reg dcaccess;
|
reg dcaccess;
|
wire dhit;
|
wire dhit;
|
wire [64:15] dtgout;
|
wire [64:15] dtgout;
|
reg wrhit;
|
reg wrhit;
|
reg wr_dcache;
|
reg wr_dcache;
|
reg [14:0] dcadr;
|
reg [14:0] dcadr;
|
|
|
// cache RAM 32Kb
|
// cache RAM 32Kb
|
// Xilinx Core Generator Component
|
|
Raptor64_dcache_ram u10
|
Raptor64_dcache_ram u10
|
(
|
(
|
.clka(clk), // input clka
|
.wclk(clk),
|
.ena(1'b1),
|
.wr(1'b1),
|
.wea(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00), // input [7 : 0] wea
|
.sel(dcaccess ? {8{ack_i}} : wrhit ? sel_o : 8'h00),
|
.addra(dcaccess ? dcadr[14:3] : adr_o[14:3]), // input [11 : 0] addra
|
.wadr(dcaccess ? dcadr[14:3] : adr_o[14:3]),
|
.dina(dcaccess ? dat_i : dat_o), // input [63 : 0] dina
|
.i(dcaccess ? dat_i : dat_o),
|
|
.rclk(~clk),
|
.clkb(~clk), // input clkb
|
.radr(pea[14:3]),
|
.addrb(pea[14:3]), // input [11 : 0] addrb
|
.o(cdat)
|
.doutb(cdat) // output [63 : 0] doutb
|
|
);
|
);
|
|
|
|
|
// Xilinx Core Generator Component
|
|
// tag RAM 512 b
|
// tag RAM 512 b
|
Raptor64_dcache_tagram u11
|
Raptor64_dcache_tagram u11
|
(
|
(
|
.clka(clk), // input clka
|
.wclk(clk),
|
.ena(dtinit | (dcadr[5:3]==3'b111)), // input ena
|
.we(dtinit | (dcaccess && ack_i && dcadr[5:3]==3'b111)),
|
.wea(dtinit | (dcaccess & ack_i)), // input [0 : 0] wea
|
.adr(dcadr[14:6]),
|
.addra(dcadr[14:6]), // input [8 : 0] addra
|
.d({~dtinit,adr_o[63:15]}),
|
.dina({~dtinit,adr_o[63:15]}), // input [49 : 0] dina
|
|
|
.rclk(~clk),
|
.clkb(~clk), // input clkb
|
.ea(pea[14:6]),
|
.addrb(pea[14:6]), // input [8 : 0] addrb
|
.tago(dtgout)
|
.doutb(dtgout) // output [49 : 0] doutb
|
|
);
|
);
|
|
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
assign dhit = (dtgout=={1'b1,pea[63:15]});
|
|
|
|
reg [ 7:0] cdata8;
|
|
reg [15:0] cdata16;
|
|
reg [31:0] cdata32;
|
|
reg [63:0] cdata64;
|
|
|
|
always @(pea or cdat)
|
|
case(pea[2:0])
|
|
3'b000: cdata8 <= cdat[ 7: 0];
|
|
3'b001: cdata8 <= cdat[15: 8];
|
|
3'b010: cdata8 <= cdat[23:16];
|
|
3'b011: cdata8 <= cdat[31:24];
|
|
3'b100: cdata8 <= cdat[39:32];
|
|
3'b101: cdata8 <= cdat[47:40];
|
|
3'b110: cdata8 <= cdat[55:48];
|
|
3'b111: cdata8 <= cdat[63:56];
|
|
endcase
|
|
|
|
always @(pea or cdat)
|
|
case(pea[2:1])
|
|
2'b00: cdata16 <= cdat[15: 0];
|
|
2'b01: cdata16 <= cdat[31:16];
|
|
2'b10: cdata16 <= cdat[47:32];
|
|
2'b11: cdata16 <= cdat[63:48];
|
|
endcase
|
|
|
|
always @(pea or cdat)
|
|
case(pea[2])
|
|
1'b0: cdata32 <= cdat[31: 0];
|
|
1'b1: cdata32 <= cdat[63:32];
|
|
endcase
|
|
|
|
always @(pea or cdat)
|
|
cdata64 <= cdat;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
reg [64:0] xData;
|
reg [64:0] xData;
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF) && dcache_on;
|
// Load word and reserve is never cached.
|
|
wire xisCacheElement = (xData[63:52] != 12'hFFD && xData[63:52]!=12'hFFF &&
|
|
xOpcode!=`LWR && !(xOpcode==`MEMNDX && xFunc6==`LWRX)) && dcache_on;
|
reg m1IsCacheElement;
|
reg m1IsCacheElement;
|
|
|
|
|
wire [127:0] mult_out;
|
wire [127:0] mult_out;
|
wire [63:0] sqrt_out;
|
wire [63:0] sqrt_out;
|
wire [63:0] div_q;
|
wire [63:0] div_q;
|
wire [63:0] div_r;
|
wire [63:0] div_r;
|
wire sqrt_done,mult_done,div_done;
|
wire sqrt_done,mult_done,div_done;
|
wire isSqrt = xIRvalid && xOpcode==`R && xFunc==`SQRT;
|
wire isSqrt =xOpcode==`R && xFunc==`SQRT;
|
|
|
isqrt #(64) u14
|
isqrt #(64) u14
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
| Line 444... |
Line 600... |
.a(a),
|
.a(a),
|
.o(sqrt_out),
|
.o(sqrt_out),
|
.done(sqrt_done)
|
.done(sqrt_done)
|
);
|
);
|
|
|
wire isMulu = xIRvalid && xOpcode==`RR && xFunc==`MULU;
|
wire isMulu = xOpcode==`RR && xFunc==`MULU;
|
wire isMuls = xIRvalid && ((xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI);
|
wire isMuls = ((xOpcode==`RR && xFunc==`MULS) || xOpcode==`MULSI);
|
wire isMuli = xIRvalid && (xOpcode==`MULSI || xOpcode==`MULUI);
|
wire isMuli = (xOpcode==`MULSI || xOpcode==`MULUI);
|
wire isMult = xIRvalid && (xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU)));
|
wire isMult = (xOpcode==`MULSI || xOpcode==`MULUI || (xOpcode==`RR && (xFunc==`MULS || xFunc==`MULU)));
|
wire isDivu = xIRvalid && (xOpcode==`RR && xFunc==`DIVU);
|
wire isDivu = (xOpcode==`RR && xFunc==`DIVU);
|
wire isDivs = xIRvalid && ((xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI);
|
wire isDivs = ((xOpcode==`RR && xFunc==`DIVS) || xOpcode==`DIVSI);
|
wire isDivi = xIRvalid && (xOpcode==`DIVSI || xOpcode==`DIVUI);
|
wire isDivi = (xOpcode==`DIVSI || xOpcode==`DIVUI);
|
wire isDiv = xIRvalid && (xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU)));
|
wire isDiv = (xOpcode==`DIVSI || xOpcode==`DIVUI || (xOpcode==`RR && (xFunc==`DIVS || xFunc==`DIVU)));
|
wire isModu = xIRvalid && (xOpcode==`RR && xFunc==`MODU);
|
wire isModu = (xOpcode==`RR && xFunc==`MODU);
|
wire isMods = xIRvalid && (xOpcode==`RR && xFunc==`MODS);
|
wire isMods = (xOpcode==`RR && xFunc==`MODS);
|
wire isMod = isModu|isMods;
|
wire isMod = isModu|isMods;
|
|
|
Raptor64Mult u18
|
Raptor64Mult u18
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
| Line 494... |
Line 650... |
|
|
wire [63:0] fpZLOut;
|
wire [63:0] fpZLOut;
|
wire [63:0] fpLooOut;
|
wire [63:0] fpLooOut;
|
wire fpLooDone;
|
wire fpLooDone;
|
|
|
|
|
/*
|
/*
|
fpZLUnit #(64) u30
|
fpZLUnit #(64) u30
|
(
|
(
|
.op(xFunc[5:0]),
|
.op(xFunc[5:0]),
|
.a(a),
|
.a(a),
|
| Line 528... |
Line 685... |
wire [63:0] d2f_result;
|
wire [63:0] d2f_result;
|
|
|
wire f2i_iop,fpmul_iop,fpdiv_iop,fpaddsub_iop,fpcmp_iop;
|
wire f2i_iop,fpmul_iop,fpdiv_iop,fpaddsub_iop,fpcmp_iop;
|
wire f2i_ovr,fpmul_ovr,fpdiv_ovr,fpaddsub_ovr;
|
wire f2i_ovr,fpmul_ovr,fpdiv_ovr,fpaddsub_ovr;
|
wire fpmul_uf,fpaddsub_uf,fpdiv_uf;
|
wire fpmul_uf,fpaddsub_uf,fpdiv_uf;
|
|
wire [11:0] fcmp_result;
|
|
|
|
`ifdef SIMD
|
|
|
|
Raptor64_fpAdd21 u61
|
|
(
|
|
.a(a[20:0]),
|
|
.b(b[20:0]),
|
|
.operation(xFunc6),
|
|
.clk(clk),
|
|
.result(daddsub_result[20:0])
|
|
);
|
|
|
|
Raptor64_fpAdd21 u62
|
|
(
|
|
.a(a[41:21]),
|
|
.b(b[41:21]),
|
|
.operation(xFunc6),
|
|
.clk(clk),
|
|
.result(daddsub_result[41:21])
|
|
);
|
|
|
|
Raptor64_fpAdd21 u63
|
|
(
|
|
.a(a[62:42]),
|
|
.b(b[62:42]),
|
|
.operation(xFunc6),
|
|
.clk(clk),
|
|
.result(daddsub_result[62:42])
|
|
);
|
|
|
|
Raptor64_fpMul21 u64
|
|
(
|
|
.a(a[20:0]),
|
|
.b(b[20:0]),
|
|
.clk(clk),
|
|
.result(dmul_result[20:0])
|
|
);
|
|
|
|
Raptor64_fpMul21 u65
|
|
(
|
|
.a(a[41:21]),
|
|
.b(b[41:21]),
|
|
.clk(clk),
|
|
.result(dmul_result[41:21])
|
|
);
|
|
|
|
Raptor64_fpMul21 u66
|
|
(
|
|
.a(a[62:42]),
|
|
.b(b[62:42]),
|
|
.clk(clk),
|
|
.result(dmul_result[62:42])
|
|
);
|
|
|
|
Raptor64_fpDiv21 u67
|
|
(
|
|
.a(a[20:0]),
|
|
.b(b[20:0]),
|
|
.clk(clk),
|
|
.result(ddiv_result[20:0])
|
|
);
|
|
|
|
Raptor64_fpDiv21 u68
|
|
(
|
|
.a(a[41:21]),
|
|
.b(b[41:21]),
|
|
.clk(clk),
|
|
.result(ddiv_result[41:21])
|
|
);
|
|
|
|
Raptor64_fpDiv21 u69
|
|
(
|
|
.a(a[62:42]),
|
|
.b(b[62:42]),
|
|
.clk(clk),
|
|
.result(ddiv_result[62:42])
|
|
);
|
|
|
|
Raptor64_fCmp21 u70
|
|
(
|
|
.a(a[20:0]),
|
|
.b(b[20:0]),
|
|
.clk(clk),
|
|
.result(fcmp_result[3:0])
|
|
);
|
|
|
|
Raptor64_fCmp21 u71
|
|
(
|
|
.a(a[41:21]),
|
|
.b(b[41:21]),
|
|
.clk(clk),
|
|
.result(fcmp_result[7:4])
|
|
);
|
|
|
|
Raptor64_fCmp21 u72
|
|
(
|
|
.a(a[62:42]),
|
|
.b(b[62:42]),
|
|
.clk(clk),
|
|
.result(fcmp_result[11:8])
|
|
);
|
|
`endif
|
|
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
// Xilinx Core Generator Components
|
// Xilinx Core Generator Components
|
|
|
Raptor64_fpCmp u60
|
Raptor64_fpCmp u60
|
| Line 605... |
Line 864... |
else begin
|
else begin
|
if (fltdone) begin
|
if (fltdone) begin
|
FPC_overx <= fp_ovr;
|
FPC_overx <= fp_ovr;
|
end
|
end
|
if (advanceX) begin
|
if (advanceX) begin
|
if (xOpcode==`FP && xIRvalid) begin
|
`ifdef SIMD
|
|
if (xOpcode==`SIMD) begin
|
|
case(xFunc6)
|
|
`SIMD_ADD: fltctr <= 6'd10;
|
|
`SIMD_SUB: fltctr <= 6'd10;
|
|
`SIMD_MUL: fltctr <= 6'd7;
|
|
`SIMD_DIV: fltctr <= 6'd19;
|
|
`SIMD_CMP: fltctr <= 6'd2;
|
|
default: fltctr <= 6'd1;
|
|
endcase
|
|
end
|
|
else
|
|
`endif
|
|
if (xOpcode==`FP) begin
|
if (xFunc6==`FDADD) // FDADD
|
if (xFunc6==`FDADD) // FDADD
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==`FDSUB) // FDSUB
|
else if (xFunc6==`FDSUB) // FDSUB
|
fltctr <= 6'd12;
|
fltctr <= 6'd12;
|
else if (xFunc6==`FDMUL) // FDMUL
|
else if (xFunc6==`FDMUL) // FDMUL
|
| Line 757... |
Line 1029... |
Raptor64_BranchHistory u6
|
Raptor64_BranchHistory u6
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.advanceX(advanceX),
|
.advanceX(advanceX),
|
.xIRvalid(xIRvalid),
|
|
.xIR(xIR),
|
.xIR(xIR),
|
.pc(pc),
|
.pc(pc),
|
.xpc(xpc),
|
.xpc(xpc),
|
.takb(takb),
|
.takb(takb),
|
.predict_taken(predict_taken)
|
.predict_taken(predict_taken)
|
| Line 813... |
Line 1084... |
wire lt = $signed(a) < $signed(b);
|
wire lt = $signed(a) < $signed(b);
|
wire lti = $signed(a) < $signed(imm);
|
wire lti = $signed(a) < $signed(imm);
|
wire ltu = a < b;
|
wire ltu = a < b;
|
wire ltui = a < imm;
|
wire ltui = a < imm;
|
|
|
always @(xOpcode or xFunc or xFunc5 or a or b or imm or xpc or aeqz or
|
always @(xOpcode or xFunc or xFunc5 or a or b or c or imm or xpc or aeqz or xFunc6 or
|
sqrt_out or cntlzo or cntloo or tick or AXC or
|
sqrt_out or cntlzo or cntloo or tick or AXC or scale or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
lt or eq or ltu or mult_out or lti or eqi or ltui or xIR or div_q or div_r or
|
shfto or masko or bcdmulo or fpLooOut or fpZLOut or m_z or m_w or
|
shfto or masko or bcdmulo or fpLooOut or fpZLOut or m_z or m_w or
|
`ifdef TLB
|
`ifdef TLB
|
PageTableAddr or BadVAddr or ASID or tlbo or
|
PageTableAddr or BadVAddr or ASID or tlbo or
|
`endif
|
`endif
|
ASID or EPC or mutex_gate or IPC or TBA or xAXC or nonICacheSeg or rm or
|
ASID or TBA or xAXC or nonICacheSeg or rm or
|
rando or errorAddress
|
rando or errorAddress or insnkey or pchistoric
|
)
|
)
|
casex(xOpcode)
|
casex(xOpcode)
|
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`SYSCALL:
|
`SYSCALL:
|
| Line 887... |
Line 1158... |
xData1[15:8] = tlbo[15:8];
|
xData1[15:8] = tlbo[15:8];
|
end
|
end
|
`PageTableAddr: xData1 = {PageTableAddr,13'd0};
|
`PageTableAddr: xData1 = {PageTableAddr,13'd0};
|
`BadVAddr: xData1 = {BadVAddr,13'd0};
|
`BadVAddr: xData1 = {BadVAddr,13'd0};
|
`endif
|
`endif
|
|
`ifdef SEGMENTATION
|
|
`CS: xData1 = {CS[xAXC],16'h0};
|
|
`DS: xData1 = {DS[xAXC],16'h0};
|
|
`ES: xData1 = {ES[xAXC],16'b0};
|
|
`SS: xData1 = {SS[xAXC],16'h0};
|
|
`endif
|
`ASID: xData1 = ASID;
|
`ASID: xData1 = ASID;
|
`Tick: xData1 = tick;
|
`Tick: xData1 = tick;
|
`EPC: xData1 = EPC[xAXC];
|
`EPC: xData1 = EPC[xAXC];
|
`IPC: xData1 = IPC[xAXC];
|
`IPC: xData1 = IPC[xAXC];
|
`TBA: xData1 = TBA;
|
`TBA: xData1 = TBA;
|
| Line 914... |
Line 1191... |
`CMGI: xData1 = mutex_gate[xIR[11:6]];
|
`CMGI: xData1 = mutex_gate[xIR[11:6]];
|
default: xData1 = 64'd0;
|
default: xData1 = 64'd0;
|
endcase
|
endcase
|
`RR:
|
`RR:
|
case(xFunc6)
|
case(xFunc6)
|
`CMP: xData1 = lt ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMP: xData1 = lt ? 64'hFFFFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMPU: xData1 = ltu ? 64'hFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`CMPU: xData1 = ltu ? 64'hFFFFFFFFFFFFFFFF : eq ? 64'd0 : 64'd1;
|
`MIN: xData1 = lt ? a : b;
|
`MIN: xData1 = lt ? a : b;
|
`MAX: xData1 = lt ? b : a;
|
`MAX: xData1 = lt ? b : a;
|
`MOVZ: xData1 = b;
|
`MOVZ: xData1 = b;
|
`MOVNZ: xData1 = b;
|
`MOVNZ: xData1 = b;
|
`MOVPL: xData1 = b;
|
`MOVPL: xData1 = b;
|
| Line 932... |
Line 1209... |
`MODS: xData1 = div_r;
|
`MODS: xData1 = div_r;
|
`BCD_MUL: xData1 = bcdmulo;
|
`BCD_MUL: xData1 = bcdmulo;
|
`MFEP: xData1 = epat[a[7:0]];
|
`MFEP: xData1 = epat[a[7:0]];
|
default: xData1 = 64'd0;
|
default: xData1 = 64'd0;
|
endcase
|
endcase
|
|
`ifdef SIMD
|
|
`SIMD:
|
|
case(xFunc6)
|
|
`SIMD_ADD: xData1 = daddsub_result;
|
|
`SIMD_SUB: xData1 = daddsub_result;
|
|
`SIMD_MUL: xData1 = dmul_result;
|
|
`SIMD_DIV: xData1 = ddiv_result;
|
|
`SIMD_CMP: xData1 = {fcmp_result[11:8],17'd0,fcmp_result[7:4],17'd0,fcmp_result[3:0]};
|
|
default: xData1 = 64'd0;
|
|
endcase
|
|
`endif
|
|
`ifdef ISIMD
|
|
`SIMD:
|
|
case(xFunc6)
|
|
`SIMD_ADD:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] + b[15: 0];
|
|
xData1[31:16] <= a[31:16] + b[31:16];
|
|
xData1[47:32] <= a[47:32] + b[47:32];
|
|
xData1[63:48] <= a[63:48] + b[63:48];
|
|
end
|
|
`SIMD_SUB:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] - b[15: 0];
|
|
xData1[31:16] <= a[31:16] - b[31:16];
|
|
xData1[47:32] <= a[47:32] - b[47:32];
|
|
xData1[63:48] <= a[63:48] - b[63:48];
|
|
end
|
|
`SIMD_MUL:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] * b[15: 0];
|
|
xData1[31:16] <= a[31:16] * b[31:16];
|
|
xData1[47:32] <= a[47:32] * b[47:32];
|
|
xData1[63:48] <= a[63:48] * b[63:48];
|
|
end
|
|
`SIMD_AND:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] & b[15: 0];
|
|
xData1[31:16] <= a[31:16] & b[31:16];
|
|
xData1[47:32] <= a[47:32] & b[47:32];
|
|
xData1[63:48] <= a[63:48] & b[63:48];
|
|
end
|
|
`SIMD_OR:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] | b[15: 0];
|
|
xData1[31:16] <= a[31:16] | b[31:16];
|
|
xData1[47:32] <= a[47:32] | b[47:32];
|
|
xData1[63:48] <= a[63:48] | b[63:48];
|
|
end
|
|
`SIMD_XOR:
|
|
begin
|
|
xData1[15: 0] <= a[15: 0] ^ b[15: 0];
|
|
xData1[31:16] <= a[31:16] ^ b[31:16];
|
|
xData1[47:32] <= a[47:32] ^ b[47:32];
|
|
xData1[63:48] <= a[63:48] ^ b[63:48];
|
|
end
|
|
endcase
|
|
`endif
|
`BTRR:
|
`BTRR:
|
case(xFunc5)
|
case(xFunc5)
|
`LOOP: xData1 = b - 64'd1;
|
`LOOP: xData1 = b - 64'd1;
|
default: xData1 = 64'd0;
|
default: xData1 = 64'd0;
|
endcase
|
endcase
|
| Line 945... |
Line 1280... |
xData1[n] = c[n] ? b[n] : a[n];
|
xData1[n] = c[n] ? b[n] : a[n];
|
end
|
end
|
`SETLO: xData1 = {{42{xIR[21]}},xIR[21:0]};
|
`SETLO: xData1 = {{42{xIR[21]}},xIR[21:0]};
|
`SETMID: xData1 = {{20{xIR[21]}},xIR[21:0],a[21:0]};
|
`SETMID: xData1 = {{20{xIR[21]}},xIR[21:0],a[21:0]};
|
`SETHI: xData1 = {xIR[19:0],a[43:0]};
|
`SETHI: xData1 = {xIR[19:0],a[43:0]};
|
`CMPI: xData1 = lti ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPI: xData1 = lti ? 64'hFFFFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPUI: xData1 = ltui ? 64'hFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`CMPUI: xData1 = ltui ? 64'hFFFFFFFFFFFFFFFF : eqi ? 64'd0 : 64'd1;
|
`MULSI: xData1 = mult_out[63:0];
|
`MULSI: xData1 = mult_out[63:0];
|
`MULUI: xData1 = mult_out[63:0];
|
`MULUI: xData1 = mult_out[63:0];
|
`DIVSI: xData1 = div_q;
|
`DIVSI: xData1 = div_q;
|
`DIVUI: xData1 = div_q;
|
`DIVUI: xData1 = div_q;
|
`INB,`INCH,`INH,`INW,`INCU,`INHU,`INBU:
|
|
xData1 = a + imm;
|
|
`OUTB,`OUTC,`OUTH,`OUTW,`OUTBC:
|
|
xData1 = a + imm;
|
|
`LW,`LH,`LC,`LB,`LHU,`LCU,`LBU,`LEA:
|
|
xData1 = a + imm;
|
|
`SW,`SH,`SC,`SB:
|
|
xData1 = a + imm;
|
|
`ifdef ADDRESS_RESERVATION
|
|
`LWR: xData1 = a + imm;
|
|
`SWC: xData1 = a + imm;
|
|
`endif
|
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
`LF,`LFD: xData1 = a + imm;
|
|
`SF,`SFD: xData1 = a + imm;
|
|
`LFP,`LFDP: xData1 = a + imm + xIR[15];
|
`LFP,`LFDP: xData1 = a + imm + xIR[15];
|
`SFP,`SFDP: xData1 = a + imm + xIR[15];
|
`SFP,`SFDP: xData1 = a + imm + xIR[15];
|
`endif
|
`endif
|
//`LP: xData1 = a + imm + xIR[15];
|
//`LP: xData1 = a + imm + xIR[15];
|
//`SP: xData1 = a + imm + xIR[15];
|
//`SP: xData1 = a + imm + xIR[15];
|
`MEMNDX:
|
`MEMNDX:
|
case(xFunc6)
|
case(xFunc6)
|
// `LPX,`LFPX,`LFDPX,`SPX,`SFPX,`SFDPX:
|
// `LPX,`LFPX,`LFDPX,`SPX,`SFPX,`SFDPX:
|
// xData1 = a + (b << scale) + imm + xIR[15];
|
// xData1 = a + (b << scale) + offset2 + xIR[15];
|
default:
|
default:
|
xData1 = a + (b << scale) + imm;
|
xData1 = a + (b << scale) + offset2;
|
endcase
|
endcase
|
`TRAPcc: xData1 = fnIncPC(xpc);
|
`TRAPcc: xData1 = fnIncPC(xpc);
|
`TRAPcci: xData1 = fnIncPC(xpc);
|
`TRAPcci: xData1 = fnIncPC(xpc);
|
`CALL: xData1 = fnIncPC(xpc);
|
`CALL: xData1 = fnIncPC(xpc);
|
`JAL: xData1 = fnIncPC(xpc);//???xpc + {xIR[19:15],2'b00};
|
`JAL: xData1 = fnIncPC(xpc);//???xpc + {xIR[19:15],2'b00};
|
| Line 1014... |
Line 1335... |
|
|
wire v_ri,v_rr;
|
wire v_ri,v_rr;
|
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xAddsubo[63]), .v(v_ri));
|
overflow u2 (.op(xOpcode==`SUBI), .a(a[63]), .b(imm[63]), .s(xAddsubo[63]), .v(v_ri));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xAddsubo[63]), .v(v_rr));
|
overflow u3 (.op(xOpcode==`RR && xFunc==`SUB), .a(a[63]), .b(b[63]), .s(xAddsubo[63]), .v(v_rr));
|
|
|
wire dbz_error = xIRvalid && (((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc6==`DIVS || xFunc6==`DIVU) && b==64'd0));
|
wire dbz_error = (((xOpcode==`DIVSI||xOpcode==`DIVUI) && imm==64'd0) || (xOpcode==`RR && (xFunc6==`DIVS || xFunc6==`DIVU) && b==64'd0));
|
wire ovr_error = xIRvalid && (((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc6==`SUB || xFunc6==`ADD)) && v_rr));
|
wire ovr_error = (((xOpcode==`ADDI || xOpcode==`SUBI) && v_ri) || ((xOpcode==`RR && (xFunc6==`SUB || xFunc6==`ADD)) && v_rr));
|
// ToDo: add more priv violations
|
// ToDo: add more priv violations
|
wire priv_violation = xIRvalid && !KernelMode && (xOpcode==`MISC &&
|
wire priv_violation = !KernelMode && (xOpcode==`MISC &&
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
(xFunc==`IRET || xFunc==`ERET || xFunc==`CLI || xFunc==`SEI ||
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI || xFunc==`IEPP
|
xFunc==`TLBP || xFunc==`TLBR || xFunc==`TLBWR || xFunc==`TLBWI || xFunc==`IEPP
|
));
|
));
|
// ToDo: detect illegal instructions in the hives (sub-opcodes)
|
// ToDo: detect illegal instructions in the hives (sub-opcodes)
|
wire illegal_insn = xIRvalid && (
|
wire illegal_insn = (
|
xOpcode==7'd19 ||
|
xOpcode==7'd19 ||
|
|
`ifndef SIMD
|
xOpcode==7'd20 ||
|
xOpcode==7'd20 ||
|
|
`endif
|
xOpcode==7'd28 ||
|
xOpcode==7'd28 ||
|
xOpcode==7'd29 ||
|
xOpcode==7'd29 ||
|
xOpcode==7'd30 ||
|
xOpcode==7'd30 ||
|
xOpcode==7'd31 ||
|
xOpcode==7'd31 ||
|
xOpcode==7'd47 ||
|
xOpcode==7'd47 ||
|
| Line 1051... |
Line 1374... |
// For performance and core size reasons, the following should really decode
|
// For performance and core size reasons, the following should really decode
|
// the opcodes in the decode stage, then pass the decoding information forward
|
// the opcodes in the decode stage, then pass the decoding information forward
|
// using regs. However the core is trickier to get working that way; decoding
|
// using regs. However the core is trickier to get working that way; decoding
|
// in multiple stages is simpler.
|
// in multiple stages is simpler.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
//wire dIsFlowCtrl =
|
|
// dOpcode==`JAL || dOpcode==`RET ||
|
|
// dOpcode==`BTRI || dOpcode==`BTRR || dOpcode==`TRAPcci || dOpcode==`TRAPcc ||
|
|
// dOpcode==`BEQI || dOpcode==`BNEI ||
|
|
// dOpcode==`BLTI || dOpcode==`BLEI || dOpcode==`BGTI || dOpcode==`BGEI ||
|
|
// dOpcode==`BLTUI || dOpcode==`BLEUI || dOpcode==`BGTUI || dOpcode==`BGEUI ||
|
|
// (dOpcode==`MISC && (dFunc==`SYSCALL || dFunc==`IRET || dFunc==`ERET))
|
|
// ;
|
|
//wire xIsFlowCtrl =
|
|
// xOpcode==`JAL || xOpcode==`RET ||
|
|
// xOpcode==`BTRI || xOpcode==`BTRR || xOpcode==`TRAPcci || xOpcode==`TRAPcc ||
|
|
// xOpcode==`BEQI || xOpcode==`BNEI ||
|
|
// xOpcode==`BLTI || xOpcode==`BLEI || xOpcode==`BGTI || xOpcode==`BGEI ||
|
|
// xOpcode==`BLTUI || xOpcode==`BLEUI || xOpcode==`BGTUI || xOpcode==`BGEUI ||
|
|
// (xOpcode==`MISC && (xFunc==`SYSCALL || xFunc==`IRET || xFunc==`ERET))
|
|
// ;
|
|
//wire m1IsFlowCtrl =
|
|
// (m1Opcode==`MISC && m1Func==`SYSCALL)
|
|
// ;
|
|
//wire m2IsFlowCtrl =
|
|
// (m2Opcode==`MISC && m2Func==`SYSCALL)
|
|
// ;
|
|
//
|
|
//
|
//wire dIsLoad = dIRvalid && (
|
//wire dIsLoad = dIRvalid && (
|
// dOpcode==`LW || dOpcode==`LH || dOpcode==`LB || dOpcode==`LWR ||
|
// dOpcode==`LW || dOpcode==`LH || dOpcode==`LB || dOpcode==`LWR ||
|
// dOpcode==`LHU || dOpcode==`LBU ||
|
// dOpcode==`LHU || dOpcode==`LBU ||
|
// dOpcode==`LC || dOpcode==`LCU || dOpcode==`LM ||
|
// dOpcode==`LC || dOpcode==`LCU || dOpcode==`LM ||
|
// dOpcode==`LF || dOpcode==`LFD || dOpcode==`LP || dOpcode==`LFP || dOpcode==`LFDP ||
|
// dOpcode==`LF || dOpcode==`LFD || dOpcode==`LP || dOpcode==`LFP || dOpcode==`LFDP ||
|
| Line 1094... |
Line 1441... |
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Pipeline advance and stall logic
|
// Pipeline advance and stall logic
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire xIsSqrt = xIRvalid && xOpcode==`R && xFunc6==`SQRT;
|
wire xIsSqrt = xOpcode==`R && xFunc6==`SQRT;
|
wire xIsMult = xIRvalid && ((xOpcode==`RR && (xFunc6==`MULU || xFunc6==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI);
|
wire xIsMult = ((xOpcode==`RR && (xFunc6==`MULU || xFunc6==`MULS)) || xOpcode==`MULSI || xOpcode==`MULUI);
|
wire xIsDiv = xIRvalid && ((xOpcode==`RR && (xFunc6==`DIVU || xFunc6==`DIVS || xFunc6==`MODU || xFunc6==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI);
|
wire xIsDiv = ((xOpcode==`RR && (xFunc6==`DIVU || xFunc6==`DIVS || xFunc6==`MODU || xFunc6==`MODS)) || xOpcode==`DIVSI || xOpcode==`DIVUI);
|
wire xIsCnt = xIRvalid && (xOpcode==`R && (xFunc6==`CTLZ || xFunc6==`CTLO || xFunc6==`CTPOP));
|
wire xIsCnt = (xOpcode==`R && (xFunc6==`CTLZ || xFunc6==`CTLO || xFunc6==`CTPOP));
|
reg m1IsCnt,m2IsCnt;
|
reg m1IsCnt,m2IsCnt;
|
reg m2IsCacheElement;
|
reg m2IsCacheElement;
|
|
|
// Have to set the xIsLoad/xIsStore flag to false when xIR is nopped out
|
// Have to set the xIsLoad/xIsStore flag to false when xIR is nopped out
|
wire xIsLoad = xIRvalid && (
|
wire xIsLoad = (
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LW || xOpcode==`LH || xOpcode==`LB || xOpcode==`LWR ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LHU || xOpcode==`LBU ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`LC || xOpcode==`LCU || xOpcode==`LM ||
|
xOpcode==`LF || xOpcode==`LFD || xOpcode==`LP || xOpcode==`LFP || xOpcode==`LFDP ||
|
xOpcode==`LF || xOpcode==`LFD || xOpcode==`LP || xOpcode==`LFP || xOpcode==`LFDP ||
|
xOpcode==`LSH || xOpcode==`LSW ||
|
xOpcode==`LSH || xOpcode==`LSW ||
|
| Line 1118... |
Line 1465... |
xFunc6==`LSHX || xFunc6==`LSWX
|
xFunc6==`LSHX || xFunc6==`LSWX
|
)) ||
|
)) ||
|
(xOpcode==`MISC && (xFunc==`SYSCALL))
|
(xOpcode==`MISC && (xFunc==`SYSCALL))
|
)
|
)
|
;
|
;
|
wire xIsStore = xIRvalid && (
|
wire xIsStore = (
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SW || xOpcode==`SH || xOpcode==`SB || xOpcode==`SC || xOpcode==`SWC || xOpcode==`SM ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SF || xOpcode==`SFD || xOpcode==`SP || xOpcode==`SFP || xOpcode==`SFDP ||
|
xOpcode==`SSH || xOpcode==`SSW || xOpcode==`STBC ||
|
xOpcode==`SSH || xOpcode==`SSW || xOpcode==`STBC ||
|
(xOpcode==`MEMNDX && (
|
(xOpcode==`MEMNDX && (
|
xFunc6==`SWX || xFunc6==`SHX || xFunc6==`SBX || xFunc6==`SCX || xFunc6==`SWCX ||
|
xFunc6==`SWX || xFunc6==`SHX || xFunc6==`SBX || xFunc6==`SCX || xFunc6==`SWCX ||
|
xFunc6==`SFX || xFunc6==`SFDX || xFunc6==`SPX ||
|
xFunc6==`SFX || xFunc6==`SFDX || xFunc6==`SPX ||
|
xFunc6==`SSHX || xFunc6==`SSWX
|
xFunc6==`SSHX || xFunc6==`SSWX
|
))
|
))
|
)
|
)
|
;
|
;
|
wire xIsSWC = xOpcode==`SWC && xIRvalid;
|
wire xIsSWC = xOpcode==`SWC;
|
wire xIsIn = xIRvalid && (
|
wire xIsIn = (
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB ||
|
xOpcode==`INW || xOpcode==`INH || xOpcode==`INCH || xOpcode==`INB ||
|
xOpcode==`INHU || xOpcode==`INCU || xOpcode==`INBU ||
|
xOpcode==`INHU || xOpcode==`INCU || xOpcode==`INBU ||
|
(xOpcode==`MEMNDX && (
|
(xOpcode==`MEMNDX && (
|
xFunc6==`INWX || xFunc6==`INHX || xFunc6==`INCX || xFunc6==`INBX ||
|
xFunc6==`INWX || xFunc6==`INHX || xFunc6==`INCX || xFunc6==`INBX ||
|
xFunc6==`INHUX || xFunc6==`INCUX || xFunc6==`INBUX
|
xFunc6==`INHUX || xFunc6==`INCUX || xFunc6==`INBUX
|
))
|
))
|
)
|
)
|
;
|
;
|
wire xIsOut = xIRvalid && (
|
wire xIsOut = (
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB ||
|
xOpcode==`OUTW || xOpcode==`OUTH || xOpcode==`OUTC || xOpcode==`OUTB ||
|
(xOpcode==`MEMNDX && (
|
(xOpcode==`MEMNDX && (
|
xFunc6==`OUTWX || xFunc6==`OUTHX || xFunc6==`OUTCX || xFunc6==`OUTBX
|
xFunc6==`OUTWX || xFunc6==`OUTHX || xFunc6==`OUTCX || xFunc6==`OUTBX
|
)))
|
)))
|
;
|
;
|
reg m1IsLoad,m1IsStore;
|
|
reg m2IsLoad,m2IsStore;
|
|
reg wIsStore;
|
|
reg m1IsOut,m1IsIn;
|
|
|
|
//wire mIsSWC = mOpcode==`SWC;
|
//wire mIsSWC = mOpcode==`SWC;
|
//reg m1IsIn;
|
//reg m1IsIn;
|
|
|
wire m2IsInW = m2Opcode==`INW;
|
wire m2IsInW = m2Opcode==`INW;
|
wire xIsIO = xIsIn || xIsOut;
|
wire xIsIO = xIsIn || xIsOut;
|
wire m1IsIO = m1IsIn || m1IsOut;
|
wire m1IsIO = m1IsIn || m1IsOut;
|
|
wire xIsSetmid = xOpcode==`SETMID;
|
|
|
wire xIsFPLoo = xIRvalid && xOpcode==`FPLOO;
|
wire xIsFPLoo = xOpcode==`FPLOO;
|
wire xIsFP = xIRvalid && xOpcode==`FP;
|
wire xIsFP = xOpcode==`FP;
|
|
wire xIsSIMD = xOpcode==`SIMD;
|
wire xneedBus = xIsIO;
|
wire xneedBus = xIsIO;
|
//wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
//wire m1needBus = (m1IsLoad & !m1IsCacheElement) || m1IsStore || m1IsIO;
|
wire m1needBus = m1IsLoad || m1IsStore || m1IsIO;
|
wire m1needBus = m1IsLoad || m1IsStore || m1IsIO;
|
wire m2needBus = m2IsLoad || m2IsStore;
|
wire m2needBus = m2IsLoad || m2IsStore;
|
|
|
wire xRtz = xRt[4:0]==5'd0;
|
wire xRtz = xRt[4:0]==5'd0;
|
wire m1Rtz = m1Rt[4:0]==5'd0;
|
wire m1Rtz = m1Rt[4:0]==5'd0;
|
wire m2Rtz = m2Rt[4:0]==5'd0;
|
wire m2Rtz = m2Rt[4:0]==5'd0;
|
|
|
//wire StallI = dIsLSPair & ~dIR[15];
|
//wire StallI = dIsLSPair & ~dIR[15];
|
|
wire intPending = nmi_edge || (irq_i & ~im); // || ITLBMiss
|
|
|
|
// Check if there are results being forwarded, to allow the pipeline to empty if result
|
|
// forwarding isn't needed.
|
|
wire tForwardingActive = tRt==dRa || tRt==dRb || tRt==dRc;
|
|
wire wForwardingActive = wRt==dRa || wRt==dRb || wRt==dRc;
|
|
wire m2ForwardingActive = m2Rt==dRa || m2Rt==dRb || m2Rt==dRc;
|
|
wire m1ForwardingActive = m1Rt==dRa || m1Rt==dRb || m1Rt==dRc;
|
|
wire xForwardingActive = xRt==dRa || xRt==dRb || xRt==dRc;
|
|
wire memCycleActive = ((iocyc_o & !(ack_i|err_i)) || (cyc_o & !(ack_i|err_i)));
|
wire StallI = 1'b0;
|
wire StallI = 1'b0;
|
|
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Stall on SWC allows rsf flag to be loaded for the next instruction
|
// Could check for dRa,dRb,dRc==0, for non-stalling
|
// Could check for dRa,dRb,dRc==0, for non-stalling
|
wire StallR = ((( xIsLoad||xIsIn||xIsCnt) && (( xRt==dRa)||( xRt==dRb)||( xRt==dRc)) && !xRtz) || xIsSWC) ||
|
wire StallR = ((( xIsLoad||xIsIn||xIsCnt) && (xForwardingActive) && !xRtz) || xIsSWC) ||
|
(((m1IsLoad||m1IsIn||m1IsCnt) && ((m1Rt==dRa)||(m1Rt==dRb)||(m1Rt==dRc)) && !m1Rtz)) ||
|
(((m1IsLoad||m1IsIn||m1IsCnt) && (m1ForwardingActive) && !m1Rtz)) ||
|
(((m2IsLoad||m2IsCnt) && ((m2Rt==dRa)||(m2Rt==dRb)||(m2Rt==dRc)) && !m2Rtz))
|
(((m2IsLoad||m2IsCnt) && (m2ForwardingActive) && !m2Rtz))
|
;
|
;
|
wire StallX = (xneedBus||xIsLoad||xIsStore) & (m1needBus|m2needBus|icaccess|dcaccess);
|
wire StallX = ((xneedBus||xIsLoad||xIsStore) & (m1needBus|m2needBus|icaccess));
|
wire StallM1 = (m1needBus & (m2needBus|icaccess|dcaccess)) ||
|
wire StallM1 = (m1needBus & (m2needBus|icaccess)) ||
|
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) // wait for a preceding store to complete
|
( m1IsLoad & m1IsCacheElement & (m2IsStore|wIsStore)) || // wait for a preceding store to complete
|
|
memCycleActive
|
;
|
;
|
wire StallM2 = m2needBus & (icaccess|dcaccess);
|
// We need to stall the pipeline stages *after* the memory load so that result forwarding
|
|
// isn't lost during a data cache load.
|
|
wire StallM2 = (m2needBus & icaccess) || (m2ForwardingActive && (((m1IsLoad & m1IsCacheElement & !dhit) || memCycleActive)));
|
|
wire StallW = (wForwardingActive && ((m1IsLoad & m1IsCacheElement & !dhit) || memCycleActive));
|
|
wire StallT = (tForwardingActive && ((m1IsLoad & m1IsCacheElement & !dhit) || memCycleActive)) || dcaccess;
|
|
|
assign advanceT = !resetA;
|
assign advanceT = (state==RUN) && !StallT;
|
assign advanceW = advanceT;
|
assign advanceW = advanceT & !StallW;
|
assign advanceM2 = advanceW && (cyc_o ? (ack_i|err_i) : 1'b1) && !StallM2;
|
assign advanceM2 = advanceW && (cyc_o ? (ack_i|err_i) : 1'b1) && !StallM2;
|
assign advanceM1 = advanceM2 &
|
assign advanceM1 = advanceM2 &
|
(iocyc_o ? (ack_i|err_i) : 1'b1) &
|
(iocyc_o ? (ack_i|err_i) : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
((m1IsLoad & m1IsCacheElement) ? dhit : 1'b1) &
|
!StallM1
|
!StallM1
|
;
|
;
|
assign advanceX = advanceM1 & (
|
assign advanceX = advanceM1 & (
|
xIsSqrt ? sqrt_done :
|
xIsSqrt ? sqrt_done :
|
xIsMult ? mult_done :
|
xIsMult ? mult_done :
|
xIsDiv ? div_done :
|
xIsDiv ? div_done :
|
|
`ifdef FLOATING_POINT
|
xIsFPLoo ? fpLooDone :
|
xIsFPLoo ? fpLooDone :
|
xIsFP ? fltdone :
|
xIsFP ? fltdone :
|
|
`endif
|
|
`ifdef SIMD
|
|
xIsSIMD ? fltdone :
|
|
`endif
|
1'b1) &
|
1'b1) &
|
!StallX;
|
!StallX;
|
assign advanceR = advanceX & !StallR;
|
assign advanceR = advanceX & !StallR;
|
assign advanceI = advanceR & (ICacheAct ? ihit : ibufrdy) & !StallI;
|
assign advanceI = advanceR & (ICacheAct ? ihit : ibufrdy) & !StallI;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Cache loading control
|
// Cache loading control
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire pipelineEmpty =
|
wire pipelineEmpty =
|
(dOpcode==`NOPI || !dIRvalid) && // and the pipeline is flushed
|
(dOpcode==`NOPI) && // and the pipeline is flushed
|
(xOpcode==`NOPI || !xIRvalid) &&
|
(xOpcode==`NOPI) &&
|
(m1Opcode==`NOPI || !m1IRvalid) &&
|
(m1Opcode==`NOPI) &&
|
(m2Opcode==`NOPI || !m2IRvalid)
|
(m2Opcode==`NOPI)
|
;
|
;
|
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
wire triggerDCacheLoad = (m1IsLoad & m1IsCacheElement & !dhit) && // there is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
(m2Opcode==`NOPI || !m2IRvalid); // and the pipeline is free of memory-ops
|
(m2Opcode==`NOPI); // and the pipeline is free of memory-ops
|
;
|
;
|
wire triggerICacheLoad1 = ICacheAct && !ihit && !triggerDCacheLoad && // There is a miss
|
wire triggerICacheLoad1 = ICacheAct && !ihit && !triggerDCacheLoad && // There is a miss
|
!(icaccess | dcaccess) && // caches are not active
|
!(icaccess | dcaccess) && // caches are not active
|
pipelineEmpty;
|
pipelineEmpty;
|
wire triggerICacheLoad2 = (!ICacheAct && !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
wire triggerICacheLoad2 = (!ICacheAct && !ibufrdy) && !triggerDCacheLoad && // There is a miss
|
| Line 1239... |
Line 1603... |
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Register file.
|
// Register file.
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
wire [63:0] nxt_a, nxt_b, nxt_c;
|
wire [63:0] nxt_a, nxt_b, nxt_c;
|
|
wire [8:0] nxt_Ra,nxt_Rb,nxt_Rc;
|
|
|
Raptor64_regfile u5
|
Raptor64_SetOperandRegs u7
|
(
|
(
|
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
|
.advanceI(advanceI),
|
.advanceR(advanceR),
|
.advanceR(advanceR),
|
.advanceW(advanceW),
|
.advanceX(advanceX),
|
.wIRvalid(wIRvalid),
|
.b(b),
|
|
.AXC(AXC),
|
|
.xAXC(xAXC),
|
|
.insn(insn),
|
|
.xIR(xIR),
|
.dRa(dRa),
|
.dRa(dRa),
|
.dRb(dRb),
|
.dRb(dRb),
|
.dRc(dRc),
|
.dRc(dRc),
|
|
.nxt_Ra(nxt_Ra),
|
|
.nxt_Rb(nxt_Rb),
|
|
.nxt_Rc(nxt_Rc)
|
|
);
|
|
|
|
syncRam512x64_1rw3r u5
|
|
(
|
|
.wrst(1'b0),
|
|
.wclk(clk),
|
|
.wce(1'b1), // advanceW
|
|
.we(1'b1),
|
|
.wadr(wRt),
|
|
.i(wData),
|
|
.wo(),
|
|
|
|
.rrsta(1'b0),
|
|
.rclka(~clk),
|
|
.rcea(advanceR),
|
|
.radra(dRa),
|
|
.roa(rfoa),
|
|
|
|
.rrstb(1'b0),
|
|
.rclkb(~clk),
|
|
.rceb(advanceR),
|
|
.radrb(dRb),
|
|
.rob(rfob),
|
|
|
|
.rrstc(1'b0),
|
|
.rclkc(~clk),
|
|
.rcec(advanceR),
|
|
.radrc(dRc),
|
|
.roc(rfoc)
|
|
);
|
|
|
|
Raptor64_BypassMux u8
|
|
(
|
.dpc(dpc),
|
.dpc(dpc),
|
|
.dRn(dRa),
|
.xRt(xRt),
|
.xRt(xRt),
|
.m1Rt(m1Rt),
|
.m1Rt(m1Rt),
|
.m2Rt(m2Rt),
|
.m2Rt(m2Rt),
|
.wRt(wRt),
|
.wRt(wRt),
|
.tRt(tRt),
|
.tRt(tRt),
|
.xData(xData[63:0]),
|
.rfo(rfoa),
|
|
.xData(xData),
|
.m1Data(m1Data),
|
.m1Data(m1Data),
|
.m2Data(m2Data),
|
.m2Data(m2Data),
|
.wData(wData),
|
.wData(wData),
|
.tData(tData),
|
.tData(tData),
|
.nxt_a(nxt_a),
|
.nxt(nxt_a)
|
.nxt_b(nxt_b),
|
|
.nxt_c(nxt_c)
|
|
);
|
);
|
|
|
Raptor64_SetOperandRegs u7
|
Raptor64_BypassMux u25
|
(
|
(
|
.rst(rst_i),
|
.dpc(dpc),
|
.clk(clk),
|
.dRn(dRb),
|
.advanceI(advanceI),
|
.xRt(xRt),
|
.advanceR(advanceR),
|
.m1Rt(m1Rt),
|
.advanceX(advanceX),
|
.m2Rt(m2Rt),
|
.b(b),
|
.wRt(wRt),
|
.AXC(AXC),
|
.tRt(tRt),
|
.xAXC(xAXC),
|
.rfo(rfob),
|
.insn(insn),
|
.xData(xData),
|
.xIR(xIR),
|
.m1Data(m1Data),
|
.dRa(dRa),
|
.m2Data(m2Data),
|
.dRb(dRb),
|
.wData(wData),
|
.dRc(dRc)
|
.tData(tData),
|
|
.nxt(nxt_b)
|
);
|
);
|
|
|
Raptor64_SetTargetRegister u8
|
Raptor64_BypassMux u24
|
(
|
(
|
.rst(rst_i),
|
.dpc(dpc),
|
.clk(clk),
|
.dRn(dRc),
|
.advanceR(advanceR),
|
.xRt(xRt),
|
.advanceX(advanceX),
|
.m1Rt(m1Rt),
|
.dIRvalid(dIRvalid),
|
.m2Rt(m2Rt),
|
.dIR(dIR),
|
.wRt(wRt),
|
.dAXC(dAXC),
|
.tRt(tRt),
|
.xRt(xRt)
|
.rfo(rfoc),
|
|
.xData(xData),
|
|
.m1Data(m1Data),
|
|
.m2Data(m2Data),
|
|
.wData(wData),
|
|
.tData(tData),
|
|
.nxt(nxt_c)
|
);
|
);
|
|
|
|
// We need to zero out xRt because it'll match in the operand bypass multiplexers if it isn't zeroed out.
|
|
//Raptor64_SetTargetRegister u8
|
|
//(
|
|
// .rst(rst_i),
|
|
// .clk(clk),
|
|
// .advanceR(advanceR),
|
|
// .advanceX(advanceX),
|
|
// .dIRvalid(dIRvalid),
|
|
// .dIR(dIR),
|
|
// .dAXC(dAXC),
|
|
// .xRt(xRt)
|
|
//);
|
|
|
reg [5:0] pchi;
|
reg [5:0] pchi;
|
vtdl #(64,64) u23
|
vtdl #(64,64) u23
|
(
|
(
|
.clk(clk),
|
.clk(clk),
|
.ce(advanceI & pccap),
|
.ce(advanceI & pccap),
|
.a(pchi),
|
.a(pchi),
|
.d(pc),
|
.d(pc),
|
.q(pchistoric)
|
.q(pchistoric)
|
);
|
);
|
|
|
|
wire isxIRQ = ((xIR[15:7]>=`EX_IRQ && xIR[15:7] < `EX_IRQ+32) || xIR[15:7]==`EX_NMI) && xIR[16];
|
|
wire isPipeIRQ = dextype==`EX_NMI || (dextype>=`EX_IRQ && dextype < `EX_IRQ+32);
|
|
wire isxNonHWI = (xIR[15:7]!=`EX_NMI &&
|
|
!(xIR[15:7]>=`EX_IRQ && xIR[15:7] < `EX_IRQ+32) &&
|
|
xIR[15:7]!=`EX_TLBI || xIR[15:7]!=`EX_TLBD);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if (rst_i) begin
|
if (rst_i) begin
|
bte_o <= 2'b00;
|
bte_o <= 2'b00;
|
cti_o <= 3'b000;
|
cti_o <= 3'b000;
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
| Line 1322... |
Line 1755... |
cstate <= IDLE;
|
cstate <= IDLE;
|
pccap <= 1'b1;
|
pccap <= 1'b1;
|
nonICacheSeg <= 32'hFFFF_FFFD;
|
nonICacheSeg <= 32'hFFFF_FFFD;
|
TBA <= 64'd0;
|
TBA <= 64'd0;
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
m1Opcode <= `NOPI;
|
dIR <= `NOP_INSN;
|
m2Opcode <= `NOPI;
|
xIR <= `NOP_INSN;
|
m1IR <= `NOP_INSN;
|
m1IR <= `NOP_INSN;
|
m2IR <= `NOP_INSN;
|
m2IR <= `NOP_INSN;
|
wIR <= `NOP_INSN;
|
wIR <= `NOP_INSN;
|
wOpcode <= `NOPI;
|
|
dIR <= `NOP_INSN;
|
|
m1IsLoad <= 1'b0;
|
m1IsLoad <= 1'b0;
|
m1IsStore <= 1'b0;
|
m1IsStore <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2IsStore <= 1'b0;
|
m2IsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
m1IsOut <= 1'b0;
|
m1IsOut <= 1'b0;
|
m1IsIn <= 1'b0;
|
m1IsIn <= 1'b0;
|
xRtZero <= 1'b0;
|
|
tRt <= 9'd0;
|
tRt <= 9'd0;
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
m2Rt <= 9'd0;
|
tData <= 64'd0;
|
tData <= 64'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
m2Data <= 64'd0;
|
m2Data <= 64'd0;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
dcaccess <= 1'b0;
|
prev_ihit <= 1'b0;
|
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
dirqf <= 1'b0;
|
dirqf <= 1'b0;
|
ipcv <= 1'b1;
|
dNmi <= 1'b0;
|
dpcv <= 1'b0;
|
xNmi <= 1'b0;
|
xpcv <= 1'b0;
|
m1Nmi <= 1'b0;
|
m1pcv <= 1'b0;
|
m2Nmi <= 1'b0;
|
m2pcv <= 1'b0;
|
|
wpcv <= 1'b0;
|
|
tick <= 64'd0;
|
tick <= 64'd0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
dAXC <= 4'd0;
|
dAXC <= 4'd0;
|
xAXC <= 4'd0;
|
xAXC <= 4'd0;
|
m1AXC <= 4'd0;
|
m1AXC <= 4'd0;
|
| Line 1374... |
Line 1801... |
xextype <= 9'h00;
|
xextype <= 9'h00;
|
m1extype <= 9'h00;
|
m1extype <= 9'h00;
|
m2extype <= 9'h00;
|
m2extype <= 9'h00;
|
wextype <= 9'h00;
|
wextype <= 9'h00;
|
textype <= 9'h00;
|
textype <= 9'h00;
|
xIR <= `NOP_INSN;
|
|
xpc <= 64'd0;
|
xpc <= 64'd0;
|
a <= 64'd0;
|
a <= 64'd0;
|
b <= 64'd0;
|
b <= 64'd0;
|
imm <= 64'd0;
|
imm <= 64'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
StatusEXL <= 16'hFFFF;
|
StatusEXL <= 16'hFFFF;
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
resetA <= 1'b1;
|
|
mutex_gate <= 64'h0;
|
mutex_gate <= 64'h0;
|
dcache_on <= 1'b0;
|
dcache_on <= 1'b0;
|
ICacheOn <= 1'b0;
|
ICacheOn <= 1'b0;
|
ibufadr <= 64'h0;
|
ibufadr <= 64'h0;
|
m1IsCacheElement <= 1'b0;
|
m1IsCacheElement <= 1'b0;
|
dtinit <= 1'b1;
|
dtinit <= 1'b1;
|
ras_sp <= 6'd63;
|
ras_sp <= 6'd63;
|
im <= 1'b1;
|
|
im1 <= 1'b1;
|
im1 <= 1'b1;
|
// These must be non-zero in order to produce random numbers
|
// These must be non-zero in order to produce random numbers
|
// We set them here in case the user doesn't bother to set them.
|
// We set them here in case the user doesn't bother to set them.
|
m_z <= 64'h0123456789ABCDEF;
|
m_z <= 64'h0123456789ABCDEF;
|
m_w <= 64'h8888888877777777;
|
m_w <= 64'h8888888877777777;
|
insnkey <= 32'd0;
|
insnkey <= 32'd0;
|
LoadNOPs <= 1'b0;
|
LoadNOPs <= 1'b0;
|
eptr <= 8'h00;
|
eptr <= 8'h00;
|
dIRvalid <= 1'b1;
|
ie_fuse <= 8'h00;
|
xIRvalid <= 1'b1;
|
|
m1IRvalid <= 1'b0;
|
|
m2IRvalid <= 1'b0;
|
|
wIRvalid <= 1'b0;
|
|
end
|
end
|
else begin
|
else begin
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// Initialize program counters
|
// Initialize program counters
|
| Line 1416... |
Line 1836... |
//---------------------------------------------------------
|
//---------------------------------------------------------
|
case(state)
|
case(state)
|
RESET:
|
RESET:
|
begin
|
begin
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
ipcv <= 1'b1;
|
|
adr_o[14:6] <= adr_o[14:6]+9'd1;
|
adr_o[14:6] <= adr_o[14:6]+9'd1;
|
if (adr_o[14:6]==9'h1FF) begin
|
if (adr_o[14:6]==9'h1FF) begin
|
dtinit <= 1'b0;
|
dtinit <= 1'b0;
|
resetA <= 1'b0;
|
|
state <= RUN;
|
state <= RUN;
|
end
|
end
|
epat[a[7:0]] <= b[3:0]; /// b=0, to make this line the same as MTEP
|
epat[a[7:0]] <= b[3:0]; /// b=0, to make this line the same as MTEP
|
a[7:0] <= a[7:0] + 8'h1;
|
a[7:0] <= a[7:0] + 8'h1;
|
end
|
end
|
RUN:
|
RUN:
|
begin
|
begin
|
|
|
|
ie_fuse <= {ie_fuse[6:0],ie_fuse[0]}; // shift counter
|
|
|
tick <= tick + 64'd1;
|
tick <= tick + 64'd1;
|
|
|
prev_nmi <= nmi_i;
|
prev_nmi <= nmi_i;
|
if (!prev_nmi & nmi_i)
|
if (!prev_nmi & nmi_i)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
| Line 1460... |
Line 1880... |
if (advanceI) begin
|
if (advanceI) begin
|
dAXC <= AXC;
|
dAXC <= AXC;
|
dextype <= `EX_NON;
|
dextype <= `EX_NON;
|
// record instruction and associated pc value
|
// record instruction and associated pc value
|
dIR <= insn;
|
dIR <= insn;
|
dIRvalid <= 1'b1;
|
|
dpc <= pc;
|
dpc <= pc;
|
dpcv <= ipcv;
|
dIm <= im;
|
|
dStatusHWI <= StatusHWI;
|
|
// Interrupt: stomp on the incoming instruction and replace it with
|
|
// a system call.
|
if (nmi_edge & !StatusHWI) begin
|
if (nmi_edge & !StatusHWI) begin
|
$display("*****************");
|
$display("*****************");
|
$display("NMI edge detected");
|
$display("NMI edge detected");
|
$display("*****************");
|
$display("*****************");
|
|
ie_fuse <= 8'h00;
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
nmi_edge <= 1'b0;
|
|
dextype <= `EX_NMI;
|
dextype <= `EX_NMI;
|
dIRvalid <= 1'b0;
|
dNmi <= 1'b1;
|
LoadNOPs <= 1'b1;
|
dIR <= {`MISC,9'd0,`EX_NMI,`SYSCALL};
|
end
|
end
|
else if (irq_i & !im & !StatusHWI) begin
|
else if (irq_i & !im & !StatusHWI) begin
|
$display("*****************");
|
$display("*****************");
|
$display("IRQ detected");
|
$display("IRQ detected");
|
$display("*****************");
|
$display("*****************");
|
bu_im <= 1'b0;
|
ie_fuse <= 8'h00;
|
im <= 1'b1;
|
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
dextype <= `EX_IRQ;
|
dIR <= {`MISC,9'd0,`EX_IRQ|irq_no,`SYSCALL};
|
dIRvalid <= 1'b0;
|
dextype <= `EX_IRQ|irq_no;
|
LoadNOPs <= 1'b1;
|
|
end
|
end
|
// Are we filling the pipeline with NOP's as a result of a previous
|
|
// hardware interrupt ?
|
|
else if (|dFip|LoadNOPs)
|
|
dIRvalid <= 1'b0;
|
|
`ifdef TLB
|
`ifdef TLB
|
else if (ITLBMiss)
|
// A TLB miss is treated like a hardware interrupt.
|
dIRvalid <= 1'b0;
|
else if (ITLBMiss) begin
|
`endif
|
|
else begin
|
|
`include "insn_dumpsc.v"
|
|
end
|
|
`ifdef TLB
|
|
if (ITLBMiss) begin
|
|
$display("TLB miss on instruction fetch.");
|
$display("TLB miss on instruction fetch.");
|
StatusEXL <= 1'b1;
|
|
BadVAddr <= pc[63:13];
|
|
dextype <= `EX_TLBI;
|
dextype <= `EX_TLBI;
|
EPC <= pc;
|
dIR <= {`MISC,9'd0,`EX_TLBI,`SYSCALL};
|
|
BadVAddr <= pc[63:13];
|
end
|
end
|
else
|
|
`endif
|
`endif
|
|
// Are we filling the pipeline with NOP's as a result of a previous
|
|
// hardware interrupt ?
|
|
else if (|dFip|LoadNOPs) begin
|
|
dIR <= `NOP_INSN;
|
|
end
|
|
else begin
|
|
`include "insn_dumpsc.v"
|
|
end
|
begin
|
begin
|
dbranch_taken <= 1'b0;
|
dbranch_taken <= 1'b0;
|
pc <= fnIncPC(pc);
|
pc <= fnIncPC(pc);
|
case(iOpcode)
|
case(iOpcode)
|
// We predict the return address by storing it in a return address stack
|
// We predict the return address by storing it in a return address stack
|
| Line 1518... |
Line 1934... |
`CALL:
|
`CALL:
|
begin
|
begin
|
ras[ras_sp] <= fnIncPC(pc);
|
ras[ras_sp] <= fnIncPC(pc);
|
ras_sp <= ras_sp - 6'd1;
|
ras_sp <= ras_sp - 6'd1;
|
pc <= jmp_tgt;
|
pc <= jmp_tgt;
|
ipcv <= 1'b1;
|
|
end
|
end
|
`RET:
|
`RET:
|
begin
|
begin
|
pc <= ras[ras_sp + 6'd1];
|
pc <= ras[ras_sp + 6'd1];
|
ras_sp <= ras_sp + 6'd1;
|
ras_sp <= ras_sp + 6'd1;
|
ipcv <= 1'b1;
|
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc <= jmp_tgt;
|
pc <= jmp_tgt;
|
ipcv <= 1'b1;
|
|
end
|
end
|
`BTRR:
|
`BTRR:
|
case(insn[4:0])
|
case(insn[4:0])
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BRA,`BNR,`BRN,`LOOP:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BRA,`BNR,`BRN,`LOOP:
|
if (predict_taken) begin
|
if (predict_taken) begin
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
// $display("Taking predicted branch: %h",{pc[63:4] + {{42{insn[24]}},insn[24:7]},insn[6:5],2'b00});
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= pc + {{52{insn[14]}},insn[14:5],2'b00};
|
pc <= pc + {{52{insn[14]}},insn[14:5],2'b00};
|
ipcv <= 1'b1;
|
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
// If doing a JAL that stores a return address in the link register, save off the return address
|
// If doing a JAL that stores a return address in the link register, save off the return address
|
| Line 1556... |
Line 1968... |
`JAL: pc <= btb[pc[7:2]];
|
`JAL: pc <= btb[pc[7:2]];
|
`BTRI:
|
`BTRI:
|
if (predict_taken) begin
|
if (predict_taken) begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= btb[pc[7:2]];
|
pc <= btb[pc[7:2]];
|
ipcv <= 1'b1;
|
|
end
|
end
|
`endif
|
`endif
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
begin
|
begin
|
if (predict_taken) begin
|
if (predict_taken) begin
|
dbranch_taken <= 1'b1;
|
dbranch_taken <= 1'b1;
|
pc <= pc + {{50{insn[19]}},insn[19:8],2'b00};
|
pc <= pc + {{50{insn[19]}},insn[19:8],2'b00};
|
ipcv <= 1'b1;
|
|
end
|
end
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceR) begin
|
else if (advanceR) begin
|
dbranch_taken <= 1'b0;
|
dextype <= #1 `EX_NON;
|
dextype <= `EX_NON;
|
dIR <= #1 `NOP_INSN;
|
dIRvalid <= 1'b0;
|
|
dpcv <= 1'b0;
|
|
end
|
end
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// RFETCH:
|
// RFETCH:
|
// Register fetch stage
|
// Register fetch stage
|
//
|
//
|
// Inputs:
|
// Inputs:
|
| Line 1592... |
Line 1999... |
// Outputs:
|
// Outputs:
|
// - x???? signals to EX stage
|
// - x???? signals to EX stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//
|
//
|
if (advanceR) begin
|
if (advanceR) begin
|
|
xIm <= dIm;
|
|
xNmi <= dNmi;
|
|
xStatusHWI <= dStatusHWI;
|
xAXC <= dAXC;
|
xAXC <= dAXC;
|
xFip <= dFip;
|
xFip <= dFip;
|
xextype <= dextype;
|
xextype <= dextype;
|
xpc <= dpc;
|
xpc <= dpc;
|
xpcv <= dpcv;
|
|
xbranch_taken <= dbranch_taken;
|
xbranch_taken <= dbranch_taken;
|
xRtZero <= 1'b0;
|
if (dOpcode==`R && dFunc==`MYST)
|
xIRvalid <= dIRvalid;
|
xIR <= nxt_c[31:0];
|
if (dOpcode==`R && dFunc==`MYST && dIRvalid)
|
|
xIR <= nxt_c;
|
|
else
|
else
|
xIR <= dIR;
|
xIR <= dIR;
|
a <= nxt_a;
|
a <= nxt_a;
|
b <= nxt_b;
|
b <= nxt_b;
|
if (dOpcode==`SHFTI)
|
if (dOpcode==`SHFTI)
|
b <= {58'd0,dIR[14:9]};
|
b <= {58'd0,dIR[14:9]};
|
c <= nxt_c;
|
c <= nxt_c;
|
|
|
case(dOpcode)
|
case(dOpcode)
|
`BTRI: imm <= {{53{dIR[10]}},dIR[10:0]};
|
`BTRI:
|
|
imm <= {{53{dIR[7]}},dIR[10:0]};
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
imm <= {{56{dIR[7]}},dIR[7:0]};
|
imm <= {{56{dIR[7]}},dIR[7:0]};
|
`RET: imm <= {49'h00000000,dIR[14:3],3'b000};
|
`MEMNDX:
|
`MEMNDX: imm <= dIR[7:6];
|
imm <= dIR[7:6];
|
default: imm <= {{49{dIR[14]}},dIR[14:0]};
|
default:
|
|
imm <= {{49{dIR[14]}},dIR[14:0]};
|
|
endcase
|
|
|
|
casex(dOpcode)
|
|
`MISC:
|
|
case(dFunc)
|
|
`SYSCALL: xRt <= 9'd0;
|
|
default: xRt <= 9'd0;
|
|
endcase
|
|
`R:
|
|
case(dFunc)
|
|
`MTSPR,`CMG,`CMGI,`EXEC:
|
|
xRt <= 9'd0;
|
|
default: xRt <= {dAXC,dIR[19:15]};
|
|
endcase
|
|
`MYST,`MUX: xRt <= {dAXC,dIR[ 9: 5]};
|
|
`SETLO: xRt <= {dAXC,dIR[26:22]};
|
|
`SETMID: xRt <= {dAXC,dIR[26:22]};
|
|
`SETHI: xRt <= {dAXC,dIR[26:22]};
|
|
`RR,`FP: xRt <= {dAXC,dIR[14:10]};
|
|
`BTRI: xRt <= 9'd0;
|
|
`BTRR:
|
|
case(dIR[4:0])
|
|
`LOOP: xRt <= {dAXC,dIR[19:15]};
|
|
default: xRt <= 9'd0;
|
|
endcase
|
|
`TRAPcc: xRt <= 9'd0;
|
|
`TRAPcci: xRt <= 9'd0;
|
|
`JMP: xRt <= 9'd00;
|
|
`CALL: xRt <= {dAXC,5'd31};
|
|
`RET: xRt <= {dAXC,5'd30};
|
|
`MEMNDX:
|
|
case(dFunc[5:0])
|
|
`LSHX,`LSWX,
|
|
`SWX,`SHX,`SCX,`SBX,`SFX,`SFDX,`SPX,`SFPX,`SFDPX,`SSHX,`SSWX,
|
|
`OUTWX,`OUTHX,`OUTCX,`OUTBX:
|
|
xRt <= 9'd0;
|
|
default: xRt <= {dAXC,dIR[14:10]};
|
|
endcase
|
|
`LSH,`LSW,
|
|
`SW,`SH,`SC,`SB,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP, // but not SWC!
|
|
`OUTW,`OUTH,`OUTC,`OUTB:
|
|
xRt <= 9'd0;
|
|
`NOPI: xRt <= 9'd0;
|
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
|
xRt <= 9'd0;
|
|
default: xRt <= {dAXC,dIR[19:15]};
|
endcase
|
endcase
|
scale <= dIR[9:8];
|
|
// if (dIsLSPair & ~dIR[15])
|
// if (dIsLSPair & ~dIR[15])
|
// dIR <= dIR|32'h8000;
|
// dIR <= dIR|32'h8000;
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceX) begin
|
else if (advanceX) begin
|
xRtZero <= #1 1'b1;
|
xRt <= #1 9'd0;
|
xextype <= #1 `EX_NON;
|
xextype <= #1 `EX_NON;
|
xbranch_taken <= #1 1'b0;
|
xIR <= #1 `NOP_INSN;
|
xIRvalid <= #1 1'b0;
|
|
xpcv <= #1 1'b0;
|
|
xFip <= #1 1'b0;
|
xFip <= #1 1'b0;
|
end
|
end
|
|
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// EXECUTE:
|
// EXECUTE:
|
| Line 1641... |
Line 2094... |
// - perform virtual to physical address translation.
|
// - perform virtual to physical address translation.
|
// Outputs:
|
// Outputs:
|
// - m1???? signals to M1 stage
|
// - m1???? signals to M1 stage
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
if (advanceX) begin
|
if (advanceX) begin
|
|
m1StatusHWI <= xStatusHWI;
|
|
m1Im <= xIm;
|
|
m1Nmi <= xNmi;
|
m1extype <= xextype;
|
m1extype <= xextype;
|
m1Fip <= xFip;
|
m1Fip <= xFip;
|
m1Func <= xFunc;
|
|
m1pcv <= xpcv;
|
|
m1pc <= xpc;
|
m1pc <= xpc;
|
m1IR <= xIR;
|
m1IR <= xIR;
|
m1IsCnt <= xIsCnt;
|
m1IsCnt <= xIsCnt;
|
m1Opcode <= xOpcode;
|
m1IsLoad <= xIsLoad;
|
m1IsLoad <= xIsLoad & xIRvalid;
|
m1IsStore <= xIsStore;
|
m1IsStore <= xIsStore & xIRvalid;
|
m1IsOut <= xIsOut;
|
m1IsOut <= xIsOut & xIRvalid;
|
m1IsIn <= xIsIn;
|
m1IsIn <= xIsIn & xIRvalid;
|
m1Rt <= xRt;
|
m1Rt <= xRtZero ? 9'd0 : xRt;
|
|
m1Data <= xData;
|
m1Data <= xData;
|
m1IsCacheElement <= xisCacheElement;
|
m1IsCacheElement <= xisCacheElement;
|
m1IRvalid <= xIRvalid;
|
|
m1AXC <= xAXC;
|
m1AXC <= xAXC;
|
if (xOpcode==`RR && xIRvalid) begin
|
if (xOpcode==`RR) begin
|
if (xFunc6==`MOVZ && !aeqz) begin
|
if (xFunc6==`MOVZ && !aeqz) begin
|
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
end
|
end
|
if (xFunc6==`MOVNZ && aeqz) begin
|
if (xFunc6==`MOVNZ && aeqz) begin
|
| Line 1677... |
Line 2129... |
m1Rt <= 9'd0;
|
m1Rt <= 9'd0;
|
m1Data <= 64'd0;
|
m1Data <= 64'd0;
|
end
|
end
|
end
|
end
|
|
|
if (xIRvalid) begin
|
begin
|
case(xOpcode)
|
case(xOpcode)
|
`MISC:
|
`MISC:
|
case(xFunc)
|
case(xFunc)
|
`SEI: im <= 1'b1;
|
`SEI: begin ie_fuse <= 8'h00; end
|
`CLI: im <= 1'b0;
|
`CLI: begin ie_fuse[0] <= 1'b1; end
|
`WAIT: m1clkoff <= 1'b1;
|
`WAIT: m1clkoff <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_ON: ICacheOn <= 1'b1;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`ICACHE_OFF: ICacheOn <= 1'b0;
|
`DCACHE_ON: dcache_on <= 1'b1;
|
`DCACHE_ON: dcache_on <= 1'b1;
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`DCACHE_OFF: dcache_on <= 1'b0;
|
`FIP: begin
|
`FIP: begin
|
dIRvalid <= 1'b0;
|
// In case we stomped on am interrupt, we have to re-enable
|
xIRvalid <= 1'b0;
|
// interrupts which were disable in the I-Stage. We go backwards
|
xRtZero <= 1'b1;
|
// in time and set the interrupt status to what it used to be
|
xpcv <= 1'b0;
|
// when this instruction is executed.
|
dpcv <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
ipcv <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
|
if (!xNmi&!dNmi) begin
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
end
|
|
xRt <= 9'd0;
|
dFip <= 1'b1;
|
dFip <= 1'b1;
|
xFip <= 1'b1;
|
xFip <= 1'b1;
|
m1Fip <= 1'b1;
|
m1Fip <= 1'b1;
|
end
|
end
|
`IEPP: begin
|
`IEPP: begin
|
eptr <= eptr + 8'd1;
|
eptr <= eptr + 8'd1;
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b0;
|
end
|
|
xRt <= 9'd0;
|
dFip <= 1'b1;
|
dFip <= 1'b1;
|
xFip <= 1'b1;
|
xFip <= 1'b1;
|
m1Fip <= 1'b1;
|
m1Fip <= 1'b1;
|
end
|
end
|
`GRAN: begin
|
`GRAN: begin
|
| Line 1724... |
Line 2182... |
m_w <= next_m_w;
|
m_w <= next_m_w;
|
end
|
end
|
`IRET:
|
`IRET:
|
if (StatusHWI) begin
|
if (StatusHWI) begin
|
StatusHWI <= 1'b0;
|
StatusHWI <= 1'b0;
|
im <= 1'b0;
|
ie_fuse[0] <= 1'b1;
|
pc <= IPC[xAXC]; //a;
|
pc <= IPC[xAXC]; //a;
|
dIRvalid <= 1'b0;
|
if (!xNmi&!dNmi) begin
|
xIRvalid <= 1'b0;
|
dIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xIR <= `NOP_INSN;
|
xpcv <= 1'b0;
|
end
|
dpcv <= 1'b0;
|
xRt <= 9'd0;
|
ipcv <= 1'b1;
|
|
end
|
end
|
`ERET:
|
`ERET:
|
if (StatusEXL[xAXC]) begin
|
if (StatusEXL[xAXC]) begin
|
StatusEXL[xAXC] <= 1'b0;
|
StatusEXL[xAXC] <= 1'b0;
|
pc <= EPC[xAXC];
|
pc <= EPC[xAXC];
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
// Note: we can't mask off the interrupts in the I-stage because this
|
// Note: we can't mask off the interrupts in the I-stage because this
|
// instruction might not be valid. Eg. a branch could occur causing
|
// instruction might not be valid. Eg. a branch could occur causing
|
// the instruction to not be executed. But we don't want to allow
|
// the instruction to not be executed. But we don't want to allow
|
// nested interrupts. We would need a stack of return addresses to
|
// nested interrupts. We would need a stack of return addresses to
|
| Line 1756... |
Line 2214... |
// a real IRQ, then we merge the two IRQ's into a single one by aborting
|
// a real IRQ, then we merge the two IRQ's into a single one by aborting
|
// the IRQ SYSCALL. If nested interrupts were happening, the IRET at the
|
// the IRQ SYSCALL. If nested interrupts were happening, the IRET at the
|
// end of the real IRQ routine would re-enable interrupts too soon.
|
// end of the real IRQ routine would re-enable interrupts too soon.
|
`SYSCALL:
|
`SYSCALL:
|
begin
|
begin
|
if ((xIR[15:7]==`EX_NMI || xIR[15:7]==`EX_IRQ) && // Is this a IRQ SYSCALL ?
|
if (isxIRQ && // Is this a software IRQ SYSCALL ?
|
((dextype==`EX_NMI || dextype==`EX_IRQ) || // Is there an interrupt in the pipeline ?
|
(isPipeIRQ || intPending)) begin // Is there an interrupt in the pipeline ? OR about to happen
|
(nmi_edge & !StatusHWI) || (irq_i & ~im & !StatusHWI))) begin // OR about to happen
|
m1IR <= `NOP_INSN; // Then turn this into a NOP
|
m1Opcode <= `NOPI; // Then turn this into a NOP
|
m1Rt <= 9'd0;
|
m1IRvalid <= 1'b0;
|
|
end
|
end
|
else begin
|
else begin
|
if (xIR[15:7]!=`EX_NMI && xIR[15:7]!=`EX_IRQ)
|
if (isxNonHWI) begin
|
StatusEXL[xAXC] <= 1'b1;
|
StatusEXL[xAXC] <= 1'b1;
|
|
StatusHWI <= xStatusHWI;
|
|
ie_fuse[0] <= ~xIm;
|
|
end
|
else begin
|
else begin
|
StatusHWI <= 1'b1;
|
StatusHWI <= 1'b1;
|
im <= 1'b1;
|
ie_fuse <= 8'h00;
|
|
if (xNmi)
|
|
nmi_edge <= 1'b0;
|
end
|
end
|
dIRvalid <= 1'b0;
|
if (!xNmi&!dNmi) begin
|
xIRvalid <= 1'b0;
|
dIR <= `NOP_INSN;
|
xRtZero <= 1'b1;
|
xIR <= `NOP_INSN;
|
xpcv <= 1'b0;
|
end
|
dpcv <= 1'b0;
|
xRt <= 9'd0;
|
ipcv <= 1'b0;
|
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
ea <= {TBA[63:12],xIR[15:7],3'b000};
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
$display("EX SYSCALL thru %h",{TBA[63:12],xIR[15:7],3'b000});
|
$display("EX SYSCALL thru %h",{TBA[63:12],xIR[15:7],3'b000});
|
end
|
end
|
end
|
end
|
| Line 1791... |
Line 2252... |
case(xFunc6)
|
case(xFunc6)
|
`EXEC:
|
`EXEC:
|
begin
|
begin
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIR <= b;
|
dIR <= b;
|
xIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xRtZero <= 1'b1;
|
ie_fuse[0] <= ~xIm;
|
xpcv <= 1'b0;
|
if (!xNmi&!dNmi) begin
|
dpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
xIR <= `NOP_INSN;
|
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`MTSPR:
|
`MTSPR:
|
begin
|
begin
|
case(xIR[11:6])
|
case(xIR[11:6])
|
`ifdef TLB
|
`ifdef TLB
|
| Line 1814... |
Line 2277... |
m_z <= a;
|
m_z <= a;
|
end
|
end
|
`SRAND2: begin
|
`SRAND2: begin
|
m_w <= a;
|
m_w <= a;
|
end
|
end
|
`INSNKEY: insnkey <= a[41:0];
|
`INSNKEY: insnkey <= a[31:0];
|
`PCHI: pchi <= a[5:0];
|
`PCHI: pchi <= a[5:0];
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
`OMG: mutex_gate[a[5:0]] <= 1'b1;
|
| Line 1840... |
Line 2303... |
`JAL:
|
`JAL:
|
`ifdef BTB
|
`ifdef BTB
|
if (dpc[63:2] != a[63:2] + imm[63:2]) begin
|
if (dpc[63:2] != a[63:2] + imm[63:2]) begin
|
pc[63:2] <= a[63:2] + imm[63:2];
|
pc[63:2] <= a[63:2] + imm[63:2];
|
btb[xpc[7:2]] <= {a[63:2] + imm[63:2],2'b00};
|
btb[xpc[7:2]] <= {a[63:2] + imm[63:2],2'b00};
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtzero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`else
|
`else
|
begin
|
begin
|
pc[63:2] <= a[63:2] + imm[63:2];
|
pc[63:2] <= a[63:2] + imm[63:2];
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`endif
|
`endif
|
// Check the pc of the instruction after the RET instruction (the dpc), to
|
// Check the pc of the instruction after the RET instruction (the dpc), to
|
// see if it's equal to the RET target. If it's the same as the target then
|
// see if it's equal to the RET target. If it's the same as the target then
|
// we predicted the RET return correctly, so there's nothing to do. Otherwise
|
// we predicted the RET return correctly, so there's nothing to do. Otherwise
|
// we need to branch to the RET location.
|
// we need to branch to the RET location.
|
`RET:
|
`RET:
|
if (dpc[63:2]!=b[63:2]) begin
|
if (dpc[63:2]!=b[63:2]) begin
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`BTRR:
|
`BTRR:
|
case(xFunc5)
|
case(xFunc5)
|
// BEQ r1,r2,label
|
// BEQ r1,r2,label
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`LOOP,`BRA,`BRN:
|
`BEQ,`BNE,`BLT,`BLE,`BGT,`BGE,`BLTU,`BLEU,`BGTU,`BGEU,`BAND,`BOR,`BNR,`LOOP,`BRA,`BRN:
|
if (!takb & xbranch_taken) begin
|
if (!takb & xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
else if (takb & !xbranch_taken) begin
|
else if (takb & !xbranch_taken) begin
|
$display("Taking branch %h",{xpc[63:2] + {{52{xIR[14]}},xIR[14:5]},2'b00});
|
$display("Taking branch %h",{xpc[63:2] + {{52{xIR[14]}},xIR[14:5]},2'b00});
|
pc[63:2] <= xpc[63:2] + {{52{xIR[14]}},xIR[14:5]};
|
pc[63:2] <= xpc[63:2] + {{52{xIR[14]}},xIR[14:5]};
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
// BEQ r1,r2,r10
|
// BEQ r1,r2,r10
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
`BEQR,`BNER,`BLTR,`BLER,`BGTR,`BGER,`BLTUR,`BLEUR,`BGTUR,`BGEUR://,`BANDR,`BORR,`BNRR:
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= c[63:2];
|
pc[63:2] <= c[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
`ifdef BTB
|
`ifdef BTB
|
btb[xpc[7:2]] <= c;
|
btb[xpc[7:2]] <= c;
|
`endif
|
`endif
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
// BEQ r1,#3,r10
|
// BEQ r1,#3,r10
|
`BTRI:
|
`BTRI:
|
| Line 1922... |
Line 2391... |
if ((xbranch_taken && b[63:2]!=dpc[63:2]) || // took branch, but not to right target
|
if ((xbranch_taken && b[63:2]!=dpc[63:2]) || // took branch, but not to right target
|
!xbranch_taken) begin // didn't take branch, and were supposed to
|
!xbranch_taken) begin // didn't take branch, and were supposed to
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
btb[xpc[7:2]] <= b;
|
btb[xpc[7:2]] <= b;
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtzero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
end
|
end
|
else if (xbranch_taken) begin // took the branch, and weren't supposed to
|
else if (xbranch_taken) begin // took the branch, and weren't supposed to
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtzero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`else
|
`else
|
if (takb) begin
|
if (takb) begin
|
pc[63:2] <= b[63:2];
|
pc[63:2] <= b[63:2];
|
pc[1:0] <= 2'b00;
|
pc[1:0] <= 2'b00;
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
`endif
|
`endif
|
// BEQI r1,#3,label
|
// BEQI r1,#3,label
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
`BEQI,`BNEI,`BLTI,`BLEI,`BGTI,`BGEI,`BLTUI,`BLEUI,`BGTUI,`BGEUI:
|
if (takb) begin
|
if (takb) begin
|
if (!xbranch_taken) begin
|
if (!xbranch_taken) begin
|
pc[63:2] <= xpc[63:2] + {{50{xIR[19]}},xIR[19:8]};
|
pc[63:2] <= xpc[63:2] + {{50{xIR[19]}},xIR[19:8]};
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
if (xbranch_taken) begin
|
if (xbranch_taken) begin
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
$display("Taking mispredicted branch %h",fnIncPC(xpc));
|
pc <= fnIncPC(xpc);
|
pc <= fnIncPC(xpc);
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b1;
|
end
|
|
xRt <= 9'd0;
|
end
|
end
|
end
|
end
|
`TRAPcc,`TRAPcci:
|
`TRAPcc,`TRAPcci:
|
if (takb) begin
|
if (takb) begin
|
StatusEXL[xAXC] <= 1'b1;
|
StatusEXL[xAXC] <= 1'b1;
|
xextype <= `EX_TRAP;
|
xextype <= `EX_TRAP;
|
dIRvalid <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
xIRvalid <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
xRtZero <= 1'b1;
|
if (!xNmi&!dNmi) begin
|
xpcv <= 1'b0;
|
dIR <= `NOP_INSN;
|
dpcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
ipcv <= 1'b0;
|
end
|
|
xRt <= 9'd0;
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
end
|
end
|
|
|
`INW:
|
`INW,`INH,`INHU,`INCH,`INCU,`INB,`INBU:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= fnSelect(xOpcode,xData[2:0]);
|
adr_o <= xData1;
|
adr_o <= xData;
|
end
|
|
`INH,`INHU:
|
|
begin
|
|
iocyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111;
|
|
adr_o <= xData1;
|
|
end
|
|
`INCH,`INCU:
|
|
begin
|
|
iocyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
case(xData1[2:1])
|
|
2'b00: sel_o <= 8'b00000011;
|
|
2'b01: sel_o <= 8'b00001100;
|
|
2'b10: sel_o <= 8'b00110000;
|
|
2'b11: sel_o <= 8'b11000000;
|
|
endcase
|
|
adr_o <= xData1;
|
|
end
|
|
`INB,`INBU:
|
|
begin
|
|
iocyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
case(xData1[2:0])
|
|
3'b000: sel_o <= 8'b00000001;
|
|
3'b001: sel_o <= 8'b00000010;
|
|
3'b010: sel_o <= 8'b00000100;
|
|
3'b011: sel_o <= 8'b00001000;
|
|
3'b100: sel_o <= 8'b00010000;
|
|
3'b101: sel_o <= 8'b00100000;
|
|
3'b110: sel_o <= 8'b01000000;
|
|
3'b111: sel_o <= 8'b10000000;
|
|
endcase
|
|
adr_o <= xData1;
|
|
end
|
end
|
`OUTW:
|
`OUTW:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= fnSelect(xOpcode,xData[2:0]);
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= b;
|
dat_o <= b;
|
end
|
end
|
`OUTH:
|
`OUTH:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= fnSelect(xOpcode,xData[2:0]);
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= {2{b[31:0]}};
|
dat_o <= {2{b[31:0]}};
|
end
|
end
|
`OUTC:
|
`OUTC:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData1[2:1])
|
sel_o <= fnSelect(xOpcode,xData[2:0]);
|
2'b00: sel_o <= 8'b00000011;
|
adr_o <= xData;
|
2'b01: sel_o <= 8'b00001100;
|
|
2'b10: sel_o <= 8'b00110000;
|
|
2'b11: sel_o <= 8'b11000000;
|
|
endcase
|
|
adr_o <= xData1;
|
|
dat_o <= {4{b[15:0]}};
|
dat_o <= {4{b[15:0]}};
|
end
|
end
|
`OUTB:
|
`OUTB:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData1[2:0])
|
sel_o <= fnSelect(xOpcode,xData[2:0]);
|
3'b000: sel_o <= 8'b00000001;
|
adr_o <= xData;
|
3'b001: sel_o <= 8'b00000010;
|
|
3'b010: sel_o <= 8'b00000100;
|
|
3'b011: sel_o <= 8'b00001000;
|
|
3'b100: sel_o <= 8'b00010000;
|
|
3'b101: sel_o <= 8'b00100000;
|
|
3'b110: sel_o <= 8'b01000000;
|
|
3'b111: sel_o <= 8'b10000000;
|
|
endcase
|
|
adr_o <= xData1;
|
|
dat_o <= {8{b[7:0]}};
|
dat_o <= {8{b[7:0]}};
|
end
|
end
|
// `OUTBC:
|
// `OUTBC:
|
// begin
|
// begin
|
// iocyc_o <= 1'b1;
|
// iocyc_o <= 1'b1;
|
| Line 2100... |
Line 2526... |
// endcase
|
// endcase
|
// adr_o <= xData1;
|
// adr_o <= xData1;
|
// dat_o <= {8{xIR[19:12]}};
|
// dat_o <= {8{xIR[19:12]}};
|
// end
|
// end
|
`LEA: begin
|
`LEA: begin
|
$display("LEA %h", xData1);
|
$display("LEA %h", xData);
|
m1Data <= xData1;
|
m1Data <= xData;
|
end
|
end
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`LF,`LFD,`LM,`LSH,`LSW,`LP,`LFP,`LFDP,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWR,`LF,`LFD,`LM,`LSH,`LSW,`LP,`LFP,`LFDP,
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM,`SSW,`SP,`SFP,`SFDP:
|
`SW,`SH,`SC,`SB,`SWC,`SF,`SFD,`SM,`SSW,`SP,`SFP,`SFDP:
|
begin
|
begin
|
m1Data <= b;
|
m1Data <= b;
|
ea <= xData1;
|
ea <= xData;
|
$display("EX MEMOP %h", xData1);
|
$display("EX MEMOP %h", xData);
|
end
|
end
|
// `STBC:
|
// `STBC:
|
// begin
|
// begin
|
// m1Data <= {8{xIR[19:12]}};
|
// m1Data <= {8{xIR[19:12]}};
|
// ea <= xData1;
|
// ea <= xData1;
|
| Line 2125... |
Line 2551... |
// ea <= xData1;
|
// ea <= xData1;
|
// end
|
// end
|
`CACHE:
|
`CACHE:
|
begin
|
begin
|
m1Data <= b;
|
m1Data <= b;
|
ea <= xData1;
|
ea <= xData;
|
case(xIR[19:15])
|
case(xIR[19:15])
|
`INVIL: ; // handled in M1 stage
|
`INVIL: ; // handled in M1 stage
|
`INVIALL: tvalid <= 128'd0;
|
`INVIALL: tvalid <= 256'd0;
|
`ICACHEON: ICacheOn <= 1'b1;
|
`ICACHEON: ICacheOn <= 1'b1;
|
`ICACHEOFF: ICacheOn <= 1'b0;
|
`ICACHEOFF: ICacheOn <= 1'b0;
|
`DCACHEON: dcache_on <= 1'b1;
|
`DCACHEON: dcache_on <= 1'b1;
|
`DCACHEOFF: dcache_on <= 1'b0;
|
`DCACHEOFF: dcache_on <= 1'b0;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
`MEMNDX:
|
`MEMNDX:
|
begin
|
begin
|
m1Opcode <= 7'd32+xFunc6;
|
m1IR[31:25] <= 7'd32+xFunc6;
|
case(xFunc6)
|
case(xFunc6)
|
`LEAX:
|
`LEAX:
|
begin
|
begin
|
$display("LEAX %h", xData1);
|
$display("LEAX %h", xData);
|
m1Data <= xData1;
|
m1Data <= xData;
|
end
|
end
|
`INWX:
|
`INWX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= xData1;
|
adr_o <= xData;
|
end
|
end
|
`INHX,`INHUX:
|
`INHX,`INHUX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= xData1;
|
adr_o <= xData;
|
end
|
end
|
`INCX,`INCUX:
|
`INCX,`INCUX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(xData1[2:1])
|
case(xData[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= xData1;
|
adr_o <= xData;
|
end
|
end
|
`INBX,`INBUX:
|
`INBX,`INBUX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(xData1[2:0])
|
case(xData[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData1;
|
adr_o <= xData;
|
end
|
end
|
`OUTWX:
|
`OUTWX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= 8'hFF;
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= c;
|
dat_o <= c;
|
end
|
end
|
`OUTHX:
|
`OUTHX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
sel_o <= xData1[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= xData[2] ? 8'b11110000 : 8'b00001111;
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= {2{c[31:0]}};
|
dat_o <= {2{c[31:0]}};
|
end
|
end
|
`OUTCX:
|
`OUTCX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData1[2:1])
|
case(xData[2:1])
|
2'b00: sel_o <= 8'b00000011;
|
2'b00: sel_o <= 8'b00000011;
|
2'b01: sel_o <= 8'b00001100;
|
2'b01: sel_o <= 8'b00001100;
|
2'b10: sel_o <= 8'b00110000;
|
2'b10: sel_o <= 8'b00110000;
|
2'b11: sel_o <= 8'b11000000;
|
2'b11: sel_o <= 8'b11000000;
|
endcase
|
endcase
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= {4{c[15:0]}};
|
dat_o <= {4{c[15:0]}};
|
end
|
end
|
`OUTBX:
|
`OUTBX:
|
begin
|
begin
|
iocyc_o <= 1'b1;
|
iocyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
we_o <= 1'b1;
|
we_o <= 1'b1;
|
case(xData1[2:0])
|
case(xData[2:0])
|
3'b000: sel_o <= 8'b00000001;
|
3'b000: sel_o <= 8'b00000001;
|
3'b001: sel_o <= 8'b00000010;
|
3'b001: sel_o <= 8'b00000010;
|
3'b010: sel_o <= 8'b00000100;
|
3'b010: sel_o <= 8'b00000100;
|
3'b011: sel_o <= 8'b00001000;
|
3'b011: sel_o <= 8'b00001000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b100: sel_o <= 8'b00010000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b101: sel_o <= 8'b00100000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b110: sel_o <= 8'b01000000;
|
3'b111: sel_o <= 8'b10000000;
|
3'b111: sel_o <= 8'b10000000;
|
endcase
|
endcase
|
adr_o <= xData1;
|
adr_o <= xData;
|
dat_o <= {8{c[7:0]}};
|
dat_o <= {8{c[7:0]}};
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
m1Data <= c;
|
m1Data <= c;
|
ea <= xData1;
|
ea <= xData;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
if (xOpcode==`FP && xIRvalid) begin
|
if (xOpcode==`FP) begin
|
case (xFunc6)
|
case (xFunc6)
|
`FDADD,`FDSUB:
|
`FDADD,`FDSUB:
|
begin
|
begin
|
fp_uf <= fpaddsub_uf;
|
fp_uf <= fpaddsub_uf;
|
fp_ovr <= fpaddsub_ovr;
|
fp_ovr <= fpaddsub_ovr;
|
| Line 2292... |
Line 2718... |
endcase
|
endcase
|
end
|
end
|
`endif
|
`endif
|
if (dbz_error) begin
|
if (dbz_error) begin
|
$display("Divide by zero error");
|
$display("Divide by zero error");
|
m1extype <= #1 `EX_DBZ;
|
|
LoadNOPs <= #1 1'b1;
|
LoadNOPs <= #1 1'b1;
|
xRtZero <= #1 1'b1;
|
// Squash a pending IRQ, but not an NMI
|
xpcv <= #1 1'b0;
|
m1extype <= #1 `EX_DBZ;
|
dpcv <= #1 1'b0;
|
StatusHWI <= xStatusHWI;
|
ipcv <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
|
if (!xNmi&!dNmi) begin
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
end
|
|
xRt <= #1 9'd0;
|
end
|
end
|
else if (ovr_error) begin
|
else if (ovr_error) begin
|
$display("Overflow error");
|
$display("Overflow error");
|
m1extype <= `EX_OFL;
|
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
xRtZero <= 1'b1;
|
m1extype <= `EX_OFL;
|
xpcv <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
dpcv <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
ipcv <= 1'b0;
|
if (!xNmi&!dNmi) begin
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
end
|
|
xRt <= #1 9'd0;
|
end
|
end
|
// else if (priv_violation) begin
|
// else if (priv_violation) begin
|
// $display("Priviledge violation");
|
// $display("Priviledge violation");
|
// m1extype <= `EX_PRIV;
|
|
// LoadNOPs <= 1'b1;
|
// LoadNOPs <= 1'b1;
|
// xRtZero <= 1'b1;
|
// if (!xNmi&!dNmi) begin
|
// xpcv <= 1'b0;
|
// m1extype <= `EX_PRIV;
|
// dpcv <= 1'b0;
|
// StatusHWI <= xStatusHWI;
|
// ipcv <= 1'b0;
|
// ie_fuse[0] <= ~xIm;
|
|
// end
|
|
// dIR <= #1 `NOP_INSN;
|
|
// xIR <= #1 `NOP_INSN;
|
|
// xRt <= #1 9'd0;
|
// end
|
// end
|
else if (illegal_insn) begin
|
else if (illegal_insn) begin
|
$display("Unimplemented Instruction");
|
$display("Unimplemented Instruction");
|
m1extype <= `EX_UNIMP_INSN;
|
|
LoadNOPs <= 1'b1;
|
LoadNOPs <= 1'b1;
|
xRtZero <= 1'b1;
|
m1extype <= `EX_UNIMP_INSN;
|
xpcv <= 1'b0;
|
StatusHWI <= xStatusHWI;
|
dpcv <= 1'b0;
|
ie_fuse[0] <= ~xIm;
|
ipcv <= 1'b0;
|
if (!xNmi&!dNmi) begin
|
|
dIR <= `NOP_INSN;
|
|
xIR <= `NOP_INSN;
|
|
end
|
|
xRt <= #1 9'd0;
|
end
|
end
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceM1) begin
|
else if (advanceM1) begin
|
m1IRvalid <= #1 1'b0;
|
m1IR <= #1 `NOP_INSN;
|
m1IsLoad <= #1 1'b0;
|
m1IsLoad <= #1 1'b0;
|
m1IsStore <= #1 1'b0;
|
m1IsStore <= #1 1'b0;
|
m1IsOut <= #1 1'b0;
|
m1IsOut <= #1 1'b0;
|
m1IsIn <= #1 1'b0;
|
m1IsIn <= #1 1'b0;
|
m1Rt <= #1 9'd0;
|
m1Rt <= #1 9'd0;
|
m1clkoff <= #1 1'b0;
|
m1clkoff <= #1 1'b0;
|
m1Fip <= #1 1'b0;
|
m1Fip <= #1 1'b0;
|
m1pcv <= #1 1'b0;
|
|
m1extype <= #1 `EX_NON;
|
m1extype <= #1 `EX_NON;
|
m1IsCnt <= #1 1'b0;
|
m1IsCnt <= #1 1'b0;
|
m1IsCacheElement <= #1 1'b0;
|
m1IsCacheElement <= #1 1'b0;
|
end
|
end
|
|
|
| Line 2361... |
Line 2799... |
// - m1???? signals
|
// - m1???? signals
|
// Outputs:
|
// Outputs:
|
// - m2???? signals to M2 stage
|
// - m2???? signals to M2 stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
if (advanceM1) begin
|
if (advanceM1) begin
|
|
m2StatusHWI <= m1StatusHWI;
|
|
m2Im <= m1Im;
|
|
m2Nmi <= m1Nmi;
|
m2extype <= m1extype;
|
m2extype <= m1extype;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
m2Data <= m1Data;
|
m2Data <= m1Data;
|
m2Fip <= m1Fip;
|
m2Fip <= m1Fip;
|
m2pc <= m1pc;
|
m2pc <= m1pc;
|
m2pcv <= m1pcv;
|
|
m2IR <= m1IR;
|
m2IR <= m1IR;
|
m2Opcode <= m1Opcode;
|
|
m2Func <= m1Func;
|
|
m2IsCnt <= m1IsCnt;
|
m2IsCnt <= m1IsCnt;
|
m2Func <= m1Func;
|
|
m2Rt <= m1Rt;
|
m2Rt <= m1Rt;
|
m2clkoff <= m1clkoff;
|
m2clkoff <= m1clkoff;
|
m2AXC <= m1AXC;
|
m2AXC <= m1AXC;
|
m2IsCacheElement <= m1IsCacheElement;
|
m2IsCacheElement <= m1IsCacheElement;
|
m2IRvalid <= m1IRvalid;
|
m2IsLoad <= m1IsLoad;
|
m2IsLoad <= m1IsLoad & m1IRvalid;
|
m2IsStore <= m2IsStore;
|
m2IsStore <= m2IsStore & m1IRvalid;
|
|
|
|
if (m1IsIO & err_i & m1IRvalid) begin
|
if (m1IsIO & err_i) begin
|
m2extype <= `EX_DBERR;
|
m2extype <= `EX_DBERR;
|
errorAddress <= adr_o;
|
errorAddress <= adr_o;
|
end
|
end
|
|
|
if (m1extype == `EX_NON && m1IRvalid) begin
|
if (m1extype == `EX_NON) begin
|
case(m1Opcode)
|
case(m1Opcode)
|
`MISC:
|
`MISC:
|
case(m1Func)
|
case(m1Func)
|
`SYSCALL:
|
`SYSCALL:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
| Line 2399... |
Line 2835... |
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin // dhit must be true
|
else begin // dhit must be true
|
$display("fetched vector: %h", {cdat[63:2],2'b00});
|
$display("fetched vector: %h", {cdat[63:2],2'b00});
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
pc <= {cdat[63:2],2'b00};
|
pc <= {cdat[63:2],2'b00};
|
ipcv <= 1'b1;
|
|
LoadNOPs <= 1'b0;
|
LoadNOPs <= 1'b0;
|
end
|
end
|
endcase
|
endcase
|
`INW:
|
`INW:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= dat_i;
|
m2Data <= data64;
|
end
|
end
|
`INH:
|
`INH:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
m2Data <= {{32{data32[31]}},data32};
|
end
|
end
|
`INHU:
|
`INHU:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
m2Data <= sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
m2Data <= data32;
|
end
|
end
|
`INCH:
|
`INCH:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
m2Data <= {{48{data16[15]}},data16};
|
8'b00000011: m2Data <= {{48{dat_i[15]}},dat_i[15: 0]};
|
|
8'b00001100: m2Data <= {{48{dat_i[31]}},dat_i[31:16]};
|
|
8'b00110000: m2Data <= {{48{dat_i[47]}},dat_i[47:32]};
|
|
8'b11000000: m2Data <= {{48{dat_i[63]}},dat_i[63:48]};
|
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`INCU:
|
`INCU:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
m2Data <= data16;
|
8'b00000011: m2Data <= dat_i[15: 0];
|
|
8'b00001100: m2Data <= dat_i[31:16];
|
|
8'b00110000: m2Data <= dat_i[47:32];
|
|
8'b11000000: m2Data <= dat_i[63:48];
|
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`INB:
|
`INB:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
m2Data <= {{56{data8[7]}},data8};
|
8'b00000001: m2Data <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
|
8'b00000010: m2Data <= {{56{dat_i[15]}},dat_i[15: 8]};
|
|
8'b00000100: m2Data <= {{56{dat_i[23]}},dat_i[23:16]};
|
|
8'b00001000: m2Data <= {{56{dat_i[31]}},dat_i[31:24]};
|
|
8'b00010000: m2Data <= {{56{dat_i[39]}},dat_i[39:32]};
|
|
8'b00100000: m2Data <= {{56{dat_i[47]}},dat_i[47:40]};
|
|
8'b01000000: m2Data <= {{56{dat_i[55]}},dat_i[55:48]};
|
|
8'b10000000: m2Data <= {{56{dat_i[63]}},dat_i[63:56]};
|
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`INBU:
|
`INBU:
|
begin
|
begin
|
iocyc_o <= 1'b0;
|
iocyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
m2Data <= data8;
|
8'b00000001: m2Data <= dat_i[ 7: 0];
|
|
8'b00000010: m2Data <= dat_i[15: 8];
|
|
8'b00000100: m2Data <= dat_i[23:16];
|
|
8'b00001000: m2Data <= dat_i[31:24];
|
|
8'b00010000: m2Data <= dat_i[39:32];
|
|
8'b00100000: m2Data <= dat_i[47:40];
|
|
8'b01000000: m2Data <= dat_i[55:48];
|
|
8'b10000000: m2Data <= dat_i[63:56];
|
|
default: m2Data <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`OUTW,`OUTH,`OUTC,`OUTB,`OUTBC:
|
`OUTW,`OUTH,`OUTC,`OUTB,`OUTBC:
|
begin
|
begin
|
iocyc_o <= #1 1'b0;
|
iocyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
we_o <= #1 1'b0;
|
we_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
end
|
end
|
`CACHE:
|
`CACHE:
|
case(m1IR[19:15])
|
case(m1IR[19:15])
|
`INVIL: tvalid[pea[12:6]] <= 1'b0;
|
`INVIL: tvalid[pea[13:6]] <= 1'b0;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
|
|
|
|
`LW,`LM,`LFD,`LSW,`LP,`LFDP:
|
`LW,`LM,`LFD,`LSW,`LP,`LFDP:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
m2Data <= cdat;
|
m2Data <= cdata64;
|
end
|
end
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
`LWR:
|
`LWR:
|
if (!m1IsCacheElement) begin
|
begin
|
rsv_o <= 1'b1;
|
rsv_o <= 1'b1;
|
resv_address <= pea[63:5];
|
resv_address <= pea[63:5];
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= 8'hFF;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
|
m2IsLoad <= 1'b0;
|
|
m2Opcode <= `NOPI;
|
|
m2Data <= cdat;
|
|
rsv_o <= 1'b1; // ???
|
|
resv_address <= pea[63:5];
|
|
end
|
|
`endif
|
`endif
|
`LH,`LF,`LFP:
|
`LH,`LF,`LFP:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
if (pea[2])
|
m2Data <= {{32{cdata32[31]}},cdata32};
|
m2Data <= {{32{cdat[31]}},cdat[31:0]};
|
|
else
|
|
m2Data <= {{32{cdat[63]}},cdat[63:32]};
|
|
end
|
end
|
|
|
`LHU,`LSH:
|
`LHU,`LSH:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
sel_o <= pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
if (pea[2])
|
m2Data <= cdata32;
|
m2Data <= {32'd0,cdat};
|
|
else
|
|
m2Data <= {32'd0,cdat[63:32]};
|
|
end
|
end
|
|
|
`LC:
|
`LC:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:1])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
2'b00: sel_o <= 8'b00000011;
|
|
2'b01: sel_o <= 8'b00001100;
|
|
2'b10: sel_o <= 8'b00110000;
|
|
2'b11: sel_o <= 8'b11000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
$display("dhit=1, cdat=%h",cdat);
|
$display("dhit=1, cdat=%h",cdat);
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
case(pea[2:1])
|
m2Data <= {{48{cdata16[15]}},cdata16};
|
2'd0: m2Data <= {{48{cdat[15]}},cdat[15:0]};
|
|
2'd1: m2Data <= {{48{cdat[31]}},cdat[31:16]};
|
|
2'd2: m2Data <= {{48{cdat[47]}},cdat[47:32]};
|
|
2'd3: m2Data <= {{48{cdat[63]}},cdat[63:48]};
|
|
endcase
|
|
end
|
end
|
|
|
`LCU:
|
`LCU:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:1])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
2'b00: sel_o <= 8'b00000011;
|
|
2'b01: sel_o <= 8'b00001100;
|
|
2'b10: sel_o <= 8'b00110000;
|
|
2'b11: sel_o <= 8'b11000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
case(pea[2:1])
|
m2Data <= cdata16;
|
2'd0: m2Data <= {48'd0,cdat[15: 0]};
|
|
2'd1: m2Data <= {48'd0,cdat[31:16]};
|
|
2'd2: m2Data <= {48'd0,cdat[47:32]};
|
|
2'd3: m2Data <= {48'd0,cdat[63:48]};
|
|
endcase
|
|
end
|
end
|
|
|
`LB:
|
`LB:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
$display("Load byte:");
|
$display("Load byte:");
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:0])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
3'b000: sel_o <= 8'b00000001;
|
|
3'b001: sel_o <= 8'b00000010;
|
|
3'b010: sel_o <= 8'b00000100;
|
|
3'b011: sel_o <= 8'b00001000;
|
|
3'b100: sel_o <= 8'b00010000;
|
|
3'b101: sel_o <= 8'b00100000;
|
|
3'b110: sel_o <= 8'b01000000;
|
|
3'b111: sel_o <= 8'b10000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
case(pea[2:0])
|
m2Data <= {{56{cdata8[7]}},cdata8};
|
3'b000: m2Data <= {{56{cdat[ 7]}},cdat[ 7: 0]};
|
|
3'b001: m2Data <= {{56{cdat[15]}},cdat[15: 8]};
|
|
3'b010: m2Data <= {{56{cdat[23]}},cdat[23:16]};
|
|
3'b011: m2Data <= {{56{cdat[31]}},cdat[31:24]};
|
|
3'b100: m2Data <= {{56{cdat[39]}},cdat[39:32]};
|
|
3'b101: m2Data <= {{56{cdat[47]}},cdat[47:40]};
|
|
3'b110: m2Data <= {{56{cdat[55]}},cdat[55:48]};
|
|
3'b111: m2Data <= {{56{cdat[63]}},cdat[63:56]};
|
|
endcase
|
|
end
|
end
|
|
|
`LBU:
|
`LBU:
|
if (!m1IsCacheElement) begin
|
if (!m1IsCacheElement) begin
|
$display("Load unsigned byte:");
|
$display("Load unsigned byte:");
|
cyc_o <= 1'b1;
|
cyc_o <= 1'b1;
|
stb_o <= 1'b1;
|
stb_o <= 1'b1;
|
case(pea[2:0])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
3'b000: sel_o <= 8'b00000001;
|
|
3'b001: sel_o <= 8'b00000010;
|
|
3'b010: sel_o <= 8'b00000100;
|
|
3'b011: sel_o <= 8'b00001000;
|
|
3'b100: sel_o <= 8'b00010000;
|
|
3'b101: sel_o <= 8'b00100000;
|
|
3'b110: sel_o <= 8'b01000000;
|
|
3'b111: sel_o <= 8'b10000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
end
|
end
|
else begin
|
else begin
|
$display("m2IsLoad <= 0");
|
$display("m2IsLoad <= 0");
|
m2IsLoad <= 1'b0;
|
m2IsLoad <= 1'b0;
|
m2Opcode <= `NOPI;
|
m2IR <= `NOP_INSN;
|
case(pea[2:0])
|
m2Data <= cdata8;
|
3'b000: m2Data <= {56'd0,cdat[ 7: 0]};
|
|
3'b001: m2Data <= {56'd0,cdat[15: 8]};
|
|
3'b010: m2Data <= {56'd0,cdat[23:16]};
|
|
3'b011: m2Data <= {56'd0,cdat[31:24]};
|
|
3'b100: m2Data <= {56'd0,cdat[39:32]};
|
|
3'b101: m2Data <= {56'd0,cdat[47:40]};
|
|
3'b110: m2Data <= {56'd0,cdat[55:48]};
|
|
3'b111: m2Data <= {56'd0,cdat[63:56]};
|
|
endcase
|
|
end
|
end
|
|
|
`SW,`SM,`SFD,`SSW,`SP,`SFDP:
|
`SW,`SM,`SFD,`SSW,`SP,`SFDP:
|
begin
|
begin
|
$display("%d SW/SM %h",tick,{pea[63:3],3'b000});
|
$display("%d SW/SM %h",tick,{pea[63:3],3'b000});
|
| Line 2695... |
Line 3027... |
resv_address <= #1 59'd0;
|
resv_address <= #1 59'd0;
|
`endif
|
`endif
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
sel_o <= #1 8'hFF;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
dat_o <= #1 m1Data;
|
dat_o <= #1 m1Data;
|
end
|
end
|
|
|
`SH,`SF,`SSH,`SFP:
|
`SH,`SF,`SSH,`SFP:
|
| Line 2711... |
Line 3043... |
resv_address <= #1 59'd0;
|
resv_address <= #1 59'd0;
|
`endif
|
`endif
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
sel_o <= #1 pea[2] ? 8'b11110000 : 8'b00001111;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
dat_o <= #1 {2{m1Data[31:0]}};
|
dat_o <= #1 {2{m1Data[31:0]}};
|
end
|
end
|
|
|
`SC:
|
`SC:
|
| Line 2728... |
Line 3060... |
resv_address <= #1 59'd0;
|
resv_address <= #1 59'd0;
|
`endif
|
`endif
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
case(pea[2:1])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
2'b00: sel_o <= #1 8'b00000011;
|
|
2'b01: sel_o <= #1 8'b00001100;
|
|
2'b10: sel_o <= #1 8'b00110000;
|
|
2'b11: sel_o <= #1 8'b11000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
dat_o <= #1 {4{m1Data[15:0]}};
|
dat_o <= #1 {4{m1Data[15:0]}};
|
end
|
end
|
|
|
`SB,`STBC:
|
`SB,`STBC:
|
| Line 2749... |
Line 3076... |
resv_address <= #1 59'd0;
|
resv_address <= #1 59'd0;
|
`endif
|
`endif
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
case(pea[2:0])
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
3'b000: sel_o <= #1 8'b00000001;
|
|
3'b001: sel_o <= #1 8'b00000010;
|
|
3'b010: sel_o <= #1 8'b00000100;
|
|
3'b011: sel_o <= #1 8'b00001000;
|
|
3'b100: sel_o <= #1 8'b00010000;
|
|
3'b101: sel_o <= #1 8'b00100000;
|
|
3'b110: sel_o <= #1 8'b01000000;
|
|
3'b111: sel_o <= #1 8'b10000000;
|
|
endcase
|
|
adr_o <= pea;
|
adr_o <= pea;
|
dat_o <= #1 {8{m1Data[7:0]}};
|
dat_o <= #1 {8{m1Data[7:0]}};
|
end
|
end
|
|
|
`ifdef ADDRESS_RESERVATION
|
`ifdef ADDRESS_RESERVATION
|
| Line 2773... |
Line 3091... |
wrhit <= #1 dhit;
|
wrhit <= #1 dhit;
|
m2Addr <= pea;
|
m2Addr <= pea;
|
cyc_o <= #1 1'b1;
|
cyc_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
stb_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
we_o <= #1 1'b1;
|
sel_o <= #1 8'hFF;
|
sel_o <= fnSelect(m1Opcode,pea[2:0]);
|
adr_o <= pea;
|
adr_o <= pea;
|
dat_o <= #1 m1Data;
|
dat_o <= #1 m1Data;
|
resv_address <= #1 59'd0;
|
resv_address <= #1 59'd0;
|
rsf <= #1 1'b1;
|
rsf <= #1 1'b1;
|
end
|
end
|
else
|
else
|
m2Opcode <= #1 `NOPI;
|
m2IR <= `NOP_INSN;
|
end
|
end
|
`endif
|
`endif
|
endcase
|
endcase
|
end
|
end
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
| Line 2793... |
Line 3111... |
// instruction and ignore the error. Otherwise set the
|
// instruction and ignore the error. Otherwise set the
|
// exception type.
|
// exception type.
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
`ifdef TLB
|
`ifdef TLB
|
if (m1IsLoad && m1Rt[4:0]==5'd0 && DTLBMiss) begin
|
if (m1IsLoad && m1Rt[4:0]==5'd0 && DTLBMiss) begin
|
m1Opcode <= `NOPI;
|
m1IR <= `NOP_INSN;
|
end
|
end
|
if ((m1IsLoad&&m1Rt[4:0]!=5'd0)|m1IsStore) begin
|
if ((m1IsLoad&&m1Rt[4:0]!=5'd0)|m1IsStore) begin
|
if (DTLBMiss) begin
|
if (DTLBMiss) begin
|
$display("DTLB miss on address: %h",ea);
|
$display("DTLB miss on address: %h",ea);
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 8'h00;
|
m1extype <= `EX_TLBD;
|
m1extype <= `EX_TLBD;
|
StatusEXL <= 1'b1;
|
StatusHWI <= 1'b1;
|
BadVAddr <= ea[63:13];
|
BadVAddr <= ea[63:13];
|
m1Opcode <= `NOPI;
|
if (!xNmi&!dNmi) begin
|
m1Rt <= 9'd0;
|
|
pc <= 64'hC;
|
|
xIR <= `NOP_INSN;
|
|
xRtzero <= 1'b1;
|
|
dIR <= `NOP_INSN;
|
dIR <= `NOP_INSN;
|
m1pcv <= 1'b0;
|
xIR <= `NOP_INSN;
|
xpcv <= 1'b0;
|
end
|
dpcv <= 1'b0;
|
m1IR <= `NOP_INSN;
|
dhwxtype <= 2'b11;
|
m1Rt <= 9'd0;
|
|
xRt <= #1 9'd0;
|
|
LoadNOPs <= 1'b1;
|
end
|
end
|
end
|
end
|
`endif
|
`endif
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceM2) begin
|
else if (advanceM2) begin
|
m2Rt <= #1 9'd0;
|
m2Rt <= #1 9'd0;
|
m2IRvalid <= 1'b0;
|
m2IR <= #1 `NOP_INSN;
|
m2IsCnt <= #1 1'b0;
|
m2IsCnt <= #1 1'b0;
|
m2IsLoad <= #1 1'b0;
|
m2IsLoad <= #1 1'b0;
|
m2IsStore <= #1 1'b0;
|
m2IsStore <= #1 1'b0;
|
m2Func <= #1 7'd0;
|
|
m2Addr <= 64'd0;
|
m2Addr <= 64'd0;
|
m2Data <= #1 64'd0;
|
m2Data <= #1 64'd0;
|
m2clkoff <= #1 1'b0;
|
m2clkoff <= #1 1'b0;
|
m2Fip <= #1 1'b0;
|
m2Fip <= #1 1'b0;
|
m2pcv <= #1 1'b0;
|
|
m2extype <= #1 `EX_NON;
|
m2extype <= #1 `EX_NON;
|
m2IsCacheElement <= 1'b0;
|
m2IsCacheElement <= 1'b0;
|
end
|
end
|
|
|
|
|
| Line 2846... |
Line 3164... |
// - w???? signals to WB stage
|
// - w???? signals to WB stage
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
if (advanceM2) begin
|
if (advanceM2) begin
|
wextype <= #1 m2extype;
|
wextype <= #1 m2extype;
|
wpc <= #1 m2pc;
|
wpc <= #1 m2pc;
|
wpcv <= #1 m2pcv;
|
|
wFip <= #1 m2Fip;
|
wFip <= #1 m2Fip;
|
wIR <= #1 m2IR;
|
wIR <= #1 m2IR;
|
wIsStore <= #1 m2IsStore & m2IRvalid;
|
wIsStore <= #1 m2IsStore;
|
wOpcode <= #1 m2Opcode;
|
|
wFunc <= #1 m2Func;
|
|
wData <= #1 m2Data;
|
wData <= #1 m2Data;
|
wRt <= #1 m2Rt;
|
wRt <= #1 m2Rt;
|
wclkoff <= #1 m2clkoff;
|
wclkoff <= #1 m2clkoff;
|
wAXC <= #1 m2AXC;
|
wAXC <= #1 m2AXC;
|
wIRvalid <= m2IRvalid;
|
|
|
|
// There's not an error is a prefetch is taking place (m2Rt=0).
|
// There's not an error is a prefetch is taking place (m2Rt=0).
|
if (((m2IsLoad&&m2Rt[4:0]!=5'd0)|m2IsStore) & err_i & m2IRvalid) begin
|
if (((m2IsLoad&&m2Rt[4:0]!=5'd0)|m2IsStore) & err_i) begin
|
wextype <= #1 `EX_DBERR;
|
wextype <= #1 `EX_DBERR;
|
errorAddress <= #1 adr_o;
|
errorAddress <= #1 adr_o;
|
end
|
end
|
|
|
if (m2extype==`EX_NON & m2IRvalid) begin
|
if (m2extype==`EX_NON) begin
|
case(m2Opcode)
|
case(m2Opcode)
|
`MISC:
|
`MISC:
|
if (m2Func==`SYSCALL)
|
if (m2Func==`SYSCALL)
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
pc <= #1 {dat_i[63:2],2'b00};
|
pc <= #1 {data64[63:2],2'b00};
|
ipcv <= 1'b1;
|
|
LoadNOPs <= 1'b0;
|
LoadNOPs <= 1'b0;
|
$display("M2 Fetched vector: %h",{dat_i[63:2],2'b00});
|
$display("M2 Fetched vector: %h",{data64[63:2],2'b00});
|
end
|
end
|
`SH,`SC,`SB,`SW,`SWC,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP:
|
`SH,`SC,`SB,`SW,`SWC,`SF,`SFD,`SSH,`SSW,`SP,`SFP,`SFDP:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
| Line 2889... |
Line 3202... |
`LH,`LF,`LSH,`LFP:
|
`LH,`LF,`LSH,`LFP:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
wData <= #1 sel_o[7] ? {{32{dat_i[63]}},dat_i[63:32]}:{{32{dat_i[31]}},dat_i[31: 0]};
|
wData <= #1 {{32{data32[31]}},data32};
|
end
|
end
|
`LW,`LWR,`LFD,`LSW,`LP,`LFDP:
|
`LW,`LWR,`LFD,`LSW,`LP,`LFDP:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
wData <= #1 dat_i;
|
wData <= #1 data64;
|
end
|
end
|
`LHU:
|
`LHU:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
wData <= #1 sel_o[7] ? dat_i[63:32] : dat_i[31: 0];
|
wData <= #1 data32;
|
end
|
end
|
`LC:
|
`LC:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
case(sel_o)
|
wData <= #1 {{48{data16[15]}},data16};
|
8'b00000011: wData <= #1 {{48{dat_i[15]}},dat_i[15: 0]};
|
|
8'b00001100: wData <= #1 {{48{dat_i[31]}},dat_i[31:16]};
|
|
8'b00110000: wData <= #1 {{48{dat_i[47]}},dat_i[47:32]};
|
|
8'b11000000: wData <= #1 {{48{dat_i[63]}},dat_i[63:48]};
|
|
default: wData <= #1 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`LCU:
|
`LCU:
|
begin
|
begin
|
cyc_o <= #1 1'b0;
|
cyc_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
stb_o <= #1 1'b0;
|
sel_o <= #1 8'h00;
|
sel_o <= #1 8'h00;
|
case(sel_o)
|
wData <= #1 data16;
|
8'b00000011: wData <= #1 dat_i[15: 0];
|
|
8'b00001100: wData <= #1 dat_i[31:16];
|
|
8'b00110000: wData <= #1 dat_i[47:32];
|
|
8'b11000000: wData <= #1 dat_i[63:48];
|
|
default: wData <= #1 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`LB:
|
`LB:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
wData <= {{56{data8[7]}},data8};
|
8'b00000001: wData <= {{56{dat_i[ 7]}},dat_i[ 7: 0]};
|
|
8'b00000010: wData <= {{56{dat_i[15]}},dat_i[15: 8]};
|
|
8'b00000100: wData <= {{56{dat_i[23]}},dat_i[23:16]};
|
|
8'b00001000: wData <= {{56{dat_i[31]}},dat_i[31:24]};
|
|
8'b00010000: wData <= {{56{dat_i[39]}},dat_i[39:32]};
|
|
8'b00100000: wData <= {{56{dat_i[47]}},dat_i[47:40]};
|
|
8'b01000000: wData <= {{56{dat_i[55]}},dat_i[55:48]};
|
|
8'b10000000: wData <= {{56{dat_i[63]}},dat_i[63:56]};
|
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
`LBU:
|
`LBU:
|
begin
|
begin
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
case(sel_o)
|
wData <= data8;
|
8'b00000001: wData <= dat_i[ 7: 0];
|
|
8'b00000010: wData <= dat_i[15: 8];
|
|
8'b00000100: wData <= dat_i[23:16];
|
|
8'b00001000: wData <= dat_i[31:24];
|
|
8'b00010000: wData <= dat_i[39:32];
|
|
8'b00100000: wData <= dat_i[47:40];
|
|
8'b01000000: wData <= dat_i[55:48];
|
|
8'b10000000: wData <= dat_i[63:56];
|
|
default: wData <= 64'hDEADDEADDEADDEAD;
|
|
endcase
|
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
// Force stack pointer to word alignment
|
// Force stack pointer to word alignment
|
if (m2Rt[4:0]==5'b11110)
|
if (m2Rt[4:0]==5'b11110)
|
| Line 2975... |
Line 3256... |
end
|
end
|
end
|
end
|
// Stage tail
|
// Stage tail
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
else if (advanceW) begin
|
else if (advanceW) begin
|
|
wIR <= #1 `NOP_INSN;
|
wextype <= `EX_NON;
|
wextype <= `EX_NON;
|
wRt <= 9'd0;
|
wRt <= 9'd0;
|
wData <= 64'd0;
|
wData <= 64'd0;
|
wIsStore <= 1'b0;
|
wIsStore <= 1'b0;
|
wIRvalid <= 1'b0;
|
|
wclkoff <= 1'b0;
|
wclkoff <= 1'b0;
|
wFip <= 1'b0;
|
wFip <= 1'b0;
|
wpcv <= 1'b0;
|
|
end
|
end
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// WRITEBACK:
|
// WRITEBACK:
|
| Line 2998... |
Line 3278... |
// Outputs:
|
// Outputs:
|
// - t???? signals
|
// - t???? signals
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
//
|
//
|
if (advanceW) begin
|
if (advanceW) begin
|
textype <= wextype;
|
// Hold onto the last register update
|
|
if (wRt[4:0]!=5'd0 && wRt[4:0]!=5'd29) begin
|
tRt <= wRt;
|
tRt <= wRt;
|
tData <= wData;
|
tData <= wData;
|
|
end
|
if (wRt!=5'd0) begin
|
if (wRt!=5'd0) begin
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
$display("Writing regfile[%d:%d] with %h", wRt[8:5],wRt[4:0], wData);
|
end
|
end
|
if (wIRvalid) begin
|
|
case(wOpcode)
|
case(wOpcode)
|
`LSH:
|
`LSH:
|
case (wRt)
|
case (wRt)
|
`SR: begin
|
`SR: begin
|
bu_im <= wData[31];
|
bu_im <= wData[31];
|
im <= wData[15];
|
if (wData[15])
|
|
ie_fuse <= 8'h00;
|
|
else
|
|
ie_fuse[0] <= 1'b1;
|
FXE <= wData[12];
|
FXE <= wData[12];
|
end
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`MISC:
|
`MISC:
|
case(wFunc)
|
case(wFunc)
|
`SYSCALL:
|
`SYSCALL:
|
if (wIR[15:7]==`EX_NMI || wIR[15:7]==`EX_IRQ)
|
if (wIR[15:7]==`EX_NMI || (wIR[15:7]>=`EX_IRQ && wIR[15:7]<`EX_IRQ+32) || wIR[15:7]==`EX_TLBI || wIR[15:7]==`EX_TLBD)
|
IPC[wAXC] <= wData;
|
IPC[wAXC] <= wData;
|
else
|
else
|
EPC[wAXC] <= wData;
|
EPC[wAXC] <= wData;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
`R:
|
`R:
|
case(wFunc6)
|
case(wFunc6)
|
`MTSPR:
|
`MTSPR:
|
case(wIR[11:6])
|
case(wIR[11:6])
|
|
`ifdef SEGMENTATION
|
|
`CS: CS[wAXC][63:16] <= wData[63:16];
|
|
`DS: DS[wAXC][63:16] <= wData[63:16];
|
|
`ES: ES[wAXC][63:16] <= wData[63:16];
|
|
`SS: SS[wAXC][63:16] <= wData[63:16];
|
|
`endif
|
`IPC: begin
|
`IPC: begin
|
$display("mtspr IPC[%d]=%h",wAXC,wData);
|
$display("mtspr IPC[%d]=%h",wAXC,wData);
|
IPC[wAXC] <= wData;
|
IPC[wAXC] <= wData;
|
end
|
end
|
`EPC: EPC[wAXC] <= wData;
|
`EPC: EPC[wAXC] <= wData;
|
default: ;
|
default: ;
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
endcase
|
end
|
|
if (wclkoff)
|
if (wclkoff)
|
clk_en <= 1'b0;
|
clk_en <= 1'b0;
|
else
|
else
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
// FIP/IEPP:
|
// FIP/IEPP:
|
| Line 3051... |
Line 3340... |
m2Fip <= 1'b0;
|
m2Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
m1Fip <= 1'b0;
|
xFip <= 1'b0;
|
xFip <= 1'b0;
|
dFip <= 1'b0;
|
dFip <= 1'b0;
|
pc <= fnIncPC(wpc);
|
pc <= fnIncPC(wpc);
|
ipcv <= 1'b1;
|
|
end
|
end
|
//---------------------------------------------------------
|
//---------------------------------------------------------
|
// WRITEBACK (WB') - part two:
|
// WRITEBACK (WB') - part two:
|
// - vector to exception handler address
|
// - vector to exception handler address
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
// In the case of a hardware interrupt (NMI/IRQ) we know
|
| Line 3075... |
Line 3363... |
`EX_RST:
|
`EX_RST:
|
begin
|
begin
|
pc <= `RESET_VECTOR;
|
pc <= `RESET_VECTOR;
|
end
|
end
|
// Hardware exceptions
|
// Hardware exceptions
|
`EX_NMI,`EX_IRQ:
|
`EX_NMI,`EX_IRQ,`EX_TLBI,`EX_TLBD,
|
begin
|
`EX_IRQ+1,`EX_IRQ+2,`EX_IRQ+3,`EX_IRQ+4,`EX_IRQ+5,`EX_IRQ+6,`EX_IRQ+7,
|
$display("Stuffing SYSCALL %d",wextype);
|
`EX_IRQ+8,`EX_IRQ+9,`EX_IRQ+10,`EX_IRQ+11,`EX_IRQ+12,`EX_IRQ+13,`EX_IRQ+14,
|
dIR <= {`MISC,5'd25,4'd0,wextype,`SYSCALL};
|
`EX_IRQ+15,`EX_IRQ+16,`EX_IRQ+17,`EX_IRQ+18,`EX_IRQ+19,`EX_IRQ+20,`EX_IRQ+21,
|
dIRvalid <= 1'b1;
|
`EX_IRQ+22,`EX_IRQ+23,`EX_IRQ+24,`EX_IRQ+25,`EX_IRQ+26,`EX_IRQ+27,`EX_IRQ+28,
|
|
`EX_IRQ+29,`EX_IRQ+30,`EX_IRQ+31:
|
|
begin
|
|
dNmi <= 1'b0;
|
|
xNmi <= 1'b0;
|
|
m1Nmi <= 1'b0;
|
|
m2Nmi <= 1'b0;
|
|
// $display("Stuffing SYSCALL %d",wextype);
|
|
// dIR <= {`MISC,9'd0,wextype,`SYSCALL};
|
// One of the following pc's MUST be valid.
|
// One of the following pc's MUST be valid.
|
// wpc will be valid if the interrupt occurred outside of a branch
|
// wpc will be valid if the interrupt occurred outside of a branch
|
// shadow. m1pc or m2pc (the branch target address) will be valid
|
// shadow. m1pc or m2pc (the branch target address) will be valid
|
// depending on where in the branch shadow the interrupt falls.
|
// depending on where in the branch shadow the interrupt falls.
|
// Syscall has a larger shadow than a branch because it loads the
|
// Syscall has a larger shadow than a branch because it loads the
|
// vector from memory. Eventually syscall flags the pc valid.
|
// vector from memory. xpc or dpc should be valid depending on
|
case(1'b1)
|
// whether or not the vector is cached. Eventually syscall flags
|
wpcv: dpc <= wpc;
|
// the pc valid. If none of the PC's are valid, then there is a
|
m2pcv: dpc <= m2pc;
|
// hardware problem.
|
m1pcv: dpc <= m1pc;
|
// dpc <= wpc;
|
xpcv: dpc <= xpc;
|
// case(1'b1)
|
dpcv: dpc <= dpc;
|
// wpcv: dpc <= wpc;
|
default: dpc <= pc;
|
// m2pcv: dpc <= m2pc;
|
endcase
|
// m1pcv: dpc <= m1pc;
|
dpcv <= 1'b1;
|
// xpcv: dpc <= xpc;
|
|
// dpcv: dpc <= dpc;
|
|
// ipcv: dpc <= pc;
|
|
// default: dpc <= `RESET_VECTOR; // Can't happen
|
|
// endcase
|
|
// dpcv <= 1'b1;
|
end
|
end
|
// Software exceptions
|
// Software exceptions
|
// We probably want to return to the excepting instruction.
|
// We probably want to return to the excepting instruction.
|
`EX_TLBD,`EX_DBERR:
|
`EX_DBERR:
|
begin
|
begin
|
pccap <= 1'b0;
|
pccap <= 1'b0;
|
dIR <= {`MISC,5'd24,4'd0,wextype,`SYSCALL};
|
dIR <= {`MISC,9'd0,wextype,`SYSCALL};
|
dIRvalid <= 1'b1;
|
|
dpc <= wpc;
|
dpc <= wpc;
|
dpcv <= 1'b1;
|
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
dIR <= {`MISC,5'd24,4'd0,wextype,`SYSCALL};
|
pccap <= 1'b0;
|
dIRvalid <= 1'b1;
|
dIR <= {`MISC,9'd0,wextype,`SYSCALL};
|
dpc <= wpc;
|
dpc <= wpc;
|
dpcv <= 1'b1;
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
// Stage tail
|
|
// Pipeline annul for when a bubble in the pipeline occurs.
|
|
// T and W advance together, meaning an else would never be executed.
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// TRAILER:
|
|
// - placeholder to allow the use of synchronous register memory
|
|
//-----------------------------------------------------------------------------
|
|
if (advanceT) begin
|
|
end
|
|
|
|
|
// Hold onto the last register update
|
|
//begin
|
|
// if (tRt[4:0]!=5'd0 && tRt[4:0]!=5'd29) begin
|
|
// uRt <= tRt;
|
|
// uData <= tData;
|
|
// end
|
|
//end
|
|
|
//=============================================================================
|
//=============================================================================
|
// Cache loader
|
// Cache loader
|
//=============================================================================
|
//=============================================================================
|
case(cstate)
|
case(cstate)
|
| Line 3176... |
Line 3471... |
if (icadr[5:3]==3'd7) begin
|
if (icadr[5:3]==3'd7) begin
|
cti_o <= 3'b000; // back to non-burst mode
|
cti_o <= 3'b000; // back to non-burst mode
|
cyc_o <= 1'b0;
|
cyc_o <= 1'b0;
|
stb_o <= 1'b0;
|
stb_o <= 1'b0;
|
sel_o <= 8'h00;
|
sel_o <= 8'h00;
|
tmem[adr_o[12:6]] <= {1'b1,adr_o[63:13]}; // This will cause ihit to go high
|
tmem[adr_o[13:6]] <= adr_o[63:14]; // This will cause ihit to go high
|
tvalid[adr_o[12:6]] <= 1'b1;
|
tvalid[adr_o[13:6]] <= 1'b1;
|
icaccess <= 1'b0;
|
icaccess <= 1'b0;
|
cstate <= IDLE;
|
cstate <= IDLE;
|
end
|
end
|
end
|
end
|
//SYSCALL 509: 00000000_00000000_11111110_10010111
|
//SYSCALL 509: 00000000_00000000_11111110_10010111
|
