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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [RaptorPIC.v] - Diff between revs 33 and 50

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Rev 33	Rev 50
Line 104...	Line 104...
`input i1, i2, i3, i4, i5, i6, i7,`	`input i1, i2, i3, i4, i5, i6, i7,`
`i8, i9, i10, i11, i12, i13, i14, i15,`	`i8, i9, i10, i11, i12, i13, i14, i15,`
`output irqo, // normally connected to the processor irq`	`output irqo, // normally connected to the processor irq`
`input nmii, // nmi input connected to nmi requester`	`input nmii, // nmi input connected to nmi requester`
`output nmio, // normally connected to the nmi of cpu`	`output nmio, // normally connected to the nmi of cpu`
`output reg [3:0] irqenc`	`output [8:0] vecno`
`);`	`);`
	`parameter pVECNO = 9'd448;`

`reg [15:0] ie; // interrupt enable register`	`reg [15:0] ie; // interrupt enable register`
`reg ack1;`	`reg ack1;`
	`reg [3:0] irqenc;`

`wire cs = cyc_i && stb_i && adr_i[23:4]==20'hDC_0FF;`	`wire cs = cyc_i && stb_i && adr_i[23:4]==20'hDC_0FF;`
`assign vol_o = cs;`	`assign vol_o = cs;`

`always @(posedge clk_i)`	`always @(posedge clk_i)`
Line 134...	Line 136...
`if (sel_i[0]) ie[dat_i[3:0]] <= adr_i[1];`	`if (sel_i[0]) ie[dat_i[3:0]] <= adr_i[1];`
`endcase`	`endcase`

`// read registers`	`// read registers`
`always @(posedge clk_i)`	`always @(posedge clk_i)`
	`begin`
	`if (irqenc!=4'd0)`
	`$display("PIC: %d",irqenc);`
`if (cs)`	`if (cs)`
`case (adr_i[2:1])`	`case (adr_i[2:1])`
`2'd0: dat_o <= {12'b0,irqenc};`	`2'd0: dat_o <= {12'b0,irqenc};`
`default: dat_o <= ie;`	`default: dat_o <= ie;`
`endcase`	`endcase`
`else`	`else`
`dat_o <= 16'h0000;`	`dat_o <= 16'h0000;`
	`end`

`assign irqo = irqenc != 4'h0;`	`assign irqo = irqenc != 4'h0;`
`assign nmio = nmii & ie[0];`	`assign nmio = nmii & ie[0];`

`// irq requests are latched on every clock edge to prevent`	`// irq requests are latched on every clock edge to prevent`
Line 168...	Line 174...
`i14&ie[14]: irqenc <= 4'd14;`	`i14&ie[14]: irqenc <= 4'd14;`
`i15&ie[15]: irqenc <= 4'd15;`	`i15&ie[15]: irqenc <= 4'd15;`
`default: irqenc <= 4'd0;`	`default: irqenc <= 4'd0;`
`endcase`	`endcase`

	`assign vecno = pVECNO\|irqenc;`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [raptor64/] [trunk/] [rtl/] [verilog/] [RaptorPIC.v] - Diff between revs 33 and 50