2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
2) Load the password byte-by-byte into the password_input port. The lenght of the password is KEY_SIZE
3) Issue 768 clocks to perform key expansion
3) Issue 768 clocks to perform key expansion
4) Now you should start receiving the pseudo-random stream via the output bus, one byte per clock. To encrypt or decrypt using RC4 you simply xor your data with the output stream.
4) Now you should start receiving the pseudo-random stream via the output bus, one byte every two clocks. The output_ready signal signals when a valid byte is present at the output K.
To encrypt or decrypt using RC4 you simply xor your data with the output stream.
Also you shouldn't use the first kb of stream because of a known RC4 vulnerability, so please discard those bytes.
Also you shouldn't use the first kb of stream because of a known RC4 vulnerability, so please discard those bytes.
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation.
After installing icarus verilog in your path, just issue:
After installing icarus verilog in your path, just issue:
