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-- 

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use work.rio_common.all;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

package TestPortPackage is

  constant ADDRESS_WIDTH : natural := 31;

  constant DATA_SIZE_MAX : natural := 32;

  type TestPortMessageWishbone is record

    writeAccess : boolean;

    address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);

    byteSelect : std_logic_vector(7 downto 0);

    length : natural range 1 to DATA_SIZE_MAX;

    data : DoublewordArray(0 to DATA_SIZE_MAX-1);

    latency : natural;

  end record;

  type TestPortMessageSymbol is record

    symbolType : std_logic_vector(1 downto 0);

    symbolContent : std_logic_vector(31 downto 0);

    ignoreIdle : boolean;

  end record;

  type TestPortMessagePacketBuffer is record

    frame : RioFrame;

    willAbort : boolean;

  end record;

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  component TestPortWishbone is

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      messageEmpty_o : out std_logic;

      messageWrite_i : in std_logic;

      message_i : in TestPortMessageWishbone;

      messageAck_o : out std_logic;

      cyc_i : in std_logic;

      stb_i : in std_logic;

      we_i : in std_logic;

      adr_i : in std_logic_vector(30 downto 0);

      sel_i : in std_logic_vector(7 downto 0);

      dat_i : in std_logic_vector(63 downto 0);

      dat_o : out std_logic_vector(63 downto 0);

      err_o : out std_logic;

      ack_o : out std_logic);

  end component;

  component TestPortPacketBuffer is

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      readEmpty_o : out std_logic;

      readWrite_i : in std_logic;

      readMessage_i : in TestPortMessagePacketBuffer;

      readAck_o : out std_logic;

      writeEmpty_o : out std_logic;

      writeWrite_i : in std_logic;

      writeMessage_i : in TestPortMessagePacketBuffer;

      writeAck_o : out std_logic;

      readFrameEmpty_o : out std_logic;

      readFrame_i : in std_logic;

      readFrameRestart_i : in std_logic;

      readFrameAborted_o : out std_logic;

      readWindowEmpty_o : out std_logic;

      readWindowReset_i : in std_logic;

      readWindowNext_i : in std_logic;

      readContentEmpty_o : out std_logic;

      readContent_i : in std_logic;

      readContentEnd_o : out std_logic;

      readContentData_o : out std_logic_vector(31 downto 0);

      writeFrame_i : in std_logic;

      writeFrameAbort_i : in std_logic;

      writeContent_i : in std_logic;

      writeContentData_i : in std_logic_vector(31 downto 0));

  end component;

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  procedure TestPortWishboneWrite(

    signal writeSignal : out std_logic;

    signal messageSignal : out TestPortMessageWishbone;

    signal ackSignal : in std_logic;

    constant writeAccess : in boolean;

    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);

    constant byteSelect : in std_logic_vector(7 downto 0);

    constant length : in natural range 1 to DATA_SIZE_MAX;

    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);

    constant latency : natural := 0);

  procedure TestPortPacketBufferWrite(

    signal writeSignal : out std_logic;

    signal messageSignal : out TestPortMessagePacketBuffer;

    signal ackSignal : in std_logic;

    constant frame : in RioFrame;

    constant willAbort : boolean := false);

end package;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

package body TestPortPackage is

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  procedure TestPortWishboneWrite(

    signal writeSignal : out std_logic;

    signal messageSignal : out TestPortMessageWishbone;

    signal ackSignal : in std_logic;

    constant writeAccess : in boolean;

    constant address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);

    constant byteSelect : in std_logic_vector(7 downto 0);

    constant length : in natural range 1 to DATA_SIZE_MAX;

    constant data : in DoublewordArray(0 to DATA_SIZE_MAX-1);

    constant latency : natural := 0) is

  begin

    writeSignal <= '1';

    messageSignal.writeAccess <= writeAccess;

    messageSignal.address <= address;

    messageSignal.byteSelect <= byteSelect;

    messageSignal.length <= length;

    messageSignal.data <= data;

    messageSignal.latency <= latency;

    wait until ackSignal = '1';

    writeSignal <= '0';

    wait until ackSignal = '0';

  end procedure;

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  procedure TestPortPacketBufferWrite(

    signal writeSignal : out std_logic;

    signal messageSignal : out TestPortMessagePacketBuffer;

    signal ackSignal : in std_logic;

    constant frame : in RioFrame;

    constant willAbort : boolean := false) is

  begin

    writeSignal <= '1';

    messageSignal.frame <= frame;

    messageSignal.willAbort <= willAbort;

    wait until ackSignal = '1';

    writeSignal <= '0';

    wait until ackSignal = '0';

  end procedure;

end package body;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library std;

use std.textio.all;

use work.rio_common.all;

use work.TestPortPackage.all;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

entity TestPortPacketBuffer is

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    readEmpty_o : out std_logic;

    readWrite_i : in std_logic;

    readMessage_i : in TestPortMessagePacketBuffer;

    readAck_o : out std_logic;

    writeEmpty_o : out std_logic;

    writeWrite_i : in std_logic;

    writeMessage_i : in TestPortMessagePacketBuffer;

    writeAck_o : out std_logic;

    readFrameEmpty_o : out std_logic;

    readFrame_i : in std_logic;

    readFrameRestart_i : in std_logic;

    readFrameAborted_o : out std_logic;

    readWindowEmpty_o : out std_logic;

    readWindowReset_i : in std_logic;

    readWindowNext_i : in std_logic;

    readContentEmpty_o : out std_logic;

    readContent_i : in std_logic;

    readContentEnd_o : out std_logic;

    readContentData_o : out std_logic_vector(31 downto 0);

    -- writeFrameFull_o is missing yes, but you can control it from the testbench directly

    -- instead.

    writeFrame_i : in std_logic;

    writeFrameAbort_i : in std_logic;

    writeContent_i : in std_logic;

    writeContentData_i : in std_logic_vector(31 downto 0));

end entity;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

architecture TestPortPacketBufferPortImpl of TestPortPacketBuffer is

  constant QUEUE_SIZE : natural := 63;

  type QueueArray is array (natural range <>) of TestPortMessagePacketBuffer;

  function QueueIndexInc(constant i : natural) return natural is

    variable returnValue : natural;

  begin

    if(i = QUEUE_SIZE) then

      returnValue := 0;

    else

      returnValue := i + 1;

    end if;

    return returnValue;

  end function;

begin

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  Reader: process

    variable frameQueue : QueueArray(0 to QUEUE_SIZE);

    variable front, back, window : natural range 0 to QUEUE_SIZE;

    variable frameIndex : natural;

  begin

    wait until areset_n = '1';

    readFrameEmpty_o <= '1';

    readFrameAborted_o <= '0';

    readWindowEmpty_o <= '1';

    readContentEmpty_o <= '1';

    readContentEnd_o <= '0';

    readContentData_o <= (others=>'0');

    front := 0;

    back := 0;

    window := 0;

    frameIndex := 0;

    readEmpty_o <= '1';

    readAck_o <= '0';

    loop

      wait until clk = '1' or readWrite_i = '1';

      if (clk'event) then

        if (readFrame_i = '1') then

          if (back /= front) then

            back := QueueIndexInc(back);

          else

            TestError("READ:BACK:reading when no frame is present");

          end if;

        end if;

        if (readFrameRestart_i = '1') then

          frameIndex := 0;

        end if;

        if (readWindowReset_i = '1') then

          window := back;

          frameIndex := 0;

        end if;

        if (readWindowNext_i = '1') then

          if (window /= front) then

            window := QueueIndexInc(window);

            frameIndex := 0;

          else

            TestError("READ:WINDOW:reading when no frame is present");

          end if;

        end if;

        if (readContent_i = '1') then

          if (back /= front) then

            if (frameIndex < frameQueue(window).frame.length) then

              readContentData_o <= frameQueue(window).frame.payload(frameIndex);

              frameIndex := frameIndex + 1;

              if (frameIndex = frameQueue(window).frame.length) then

                readContentEnd_o <= '1';

              else

                readContentEnd_o <= '0';

              end if;

            else

              TestError("READ:CONTENT:reading when frame has ended");

            end if;

          else

            TestError("READ:CONTENT:reading when no frame is present");

          end if;

        end if;

        if (front = back) then

          readFrameEmpty_o <= '1';

        else

          readFrameEmpty_o <= '0';

        end if;

        if (front = window) then

          readWindowEmpty_o <= '1';

          readContentEmpty_o <= '1';

        else

          readWindowEmpty_o <= '0';

          if (frameIndex /= frameQueue(window).frame.length) then

            readContentEmpty_o <= '0';

          else

            readContentEmpty_o <= '1';

          end if;

        end if;

        if (front = back) then

          readEmpty_o <= '1';

        else

          readEmpty_o <= '0';

        end if;

      elsif (readWrite_i'event) then

        frameQueue(front) := readMessage_i;

        front := QueueIndexInc(front);

        readEmpty_o <= '0';

        readAck_o <= '1';

        wait until readWrite_i = '0';

        readAck_o <= '0';

      end if;

    end loop;

  end process;

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  Writer: process

    variable frameQueue : QueueArray(0 to QUEUE_SIZE);

    variable front, back : natural range 0 to QUEUE_SIZE;

    variable frameIndex : natural range 0 to 69;

  begin

    wait until areset_n = '1';

    writeEmpty_o <= '1';

    writeAck_o <= '0';

    front := 0;

    back := 0;

    frameIndex := 0;

    loop

      wait until clk = '1' or writeWrite_i = '1';

      if (clk'event) then

        if (writeFrame_i = '1') then

          if (frameIndex = 0) then

            TestError("WRITE:Empty frame written.");

          end if;

          if (frameIndex /= frameQueue(back).frame.length) then

            TestError("WRITE:Frame with unmatching length was written.");

          end if;

          if (back /= front) then

            back := QueueIndexInc(back);

          else

            TestError("WRITE:Unexpected frame written.");

          end if;

          frameIndex := 0;

        end if;

        if (writeFrameAbort_i = '1') then

          if (back /= front) then

            if (frameQueue(back).willAbort) then

              TestCompare(frameIndex,

                          frameQueue(back).frame.length,

                          "frameIndex abort");

              back := QueueIndexInc(back);

            else

              TestError("WRITE:Not expecting this frame to abort.");

            end if;

          end if;

          frameIndex := 0;

        end if;

        if (writeContent_i = '1') then

          if (frameIndex < frameQueue(back).frame.length) then

            TestCompare(writeContentData_i,

                        frameQueue(back).frame.payload(frameIndex),

                        "frame content");

            frameIndex := frameIndex + 1;

          else

            TestError("WRITE:Receiving more frame content than expected.");

          end if;

        end if;

        if (front = back) then

          writeEmpty_o <= '1';

        else

          writeEmpty_o <= '0';

        end if;

      elsif (writeWrite_i'event) then

        frameQueue(front) := writeMessage_i;

        front := QueueIndexInc(front);

        writeEmpty_o <= '0';

        writeAck_o <= '1';

        wait until writeWrite_i = '0';

        writeAck_o <= '0';

      end if;

    end loop;

  end process;

end architecture;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library std;

use std.textio.all;

use work.rio_common.all;

use work.TestPortPackage.all;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

entity TestPortWishbone is

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    messageEmpty_o : out std_logic;

    messageWrite_i : in std_logic;

    message_i : in TestPortMessageWishbone;

    messageAck_o : out std_logic;

    cyc_i : in std_logic;

    stb_i : in std_logic;

    we_i : in std_logic;

    adr_i : in std_logic_vector(30 downto 0);

    sel_i : in std_logic_vector(7 downto 0);

    dat_i : in std_logic_vector(63 downto 0);

    dat_o : out std_logic_vector(63 downto 0);

    err_o : out std_logic;

    ack_o : out std_logic);

end entity;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

architecture TestPortWishboneImpl of TestPortWishbone is

  constant QUEUE_SIZE : natural := 63;

  type QueueArray is array (natural range <>) of TestPortMessageWishbone;

  function QueueIndexInc(constant i : natural) return natural is

    variable returnValue : natural;

  begin

    if(i = QUEUE_SIZE) then

      returnValue := 0;

    else

      returnValue := i + 1;

    end if;

    return returnValue;

  end function;

begin

  -----------------------------------------------------------------------------

  -- 

  -----------------------------------------------------------------------------

  Slave: process

    variable queue : QueueArray(0 to QUEUE_SIZE);

    variable front, back : natural range 0 to QUEUE_SIZE;

    variable cyclePosition : natural;

    variable latencyCounter : natural;

  begin

    wait until areset_n = '1';

    messageEmpty_o <= '1';

    messageAck_o <= '0';

    dat_o <= (others=>'U');

    err_o <= '0';

    ack_o <= '0';

    front := 0;

    back := 0;

    cyclePosition := 0;

    latencyCounter := 0;

    loop

      wait until clk = '1' or messageWrite_i = '1';

      if (clk'event) then

        if (cyc_i = '1') then

          if (front /= back) then

            if (stb_i = '1') then

              if (latencyCounter <= queue(back).latency) then

                TestCompare(stb_i, '1', "stb_i");

                if (queue(back).writeAccess) then

                  TestCompare(we_i, '1', "we_i");

                else

                  TestCompare(we_i, '0', "we_i");

                end if;

                TestCompare(adr_i, std_logic_vector(unsigned(queue(back).address)+cyclePosition), "adr_i");

                TestCompare(sel_i, queue(back).byteSelect, "sel_i");

                if (queue(back).writeAccess) then

                  TestCompare(dat_i, queue(back).data(cyclePosition), "dat_i");

                end if;

              end if;

              if (latencyCounter < queue(back).latency) then

                dat_o <= (others=>'U');

                ack_o <= '0';

                latencyCounter := latencyCounter + 1;

              elsif (latencyCounter = queue(back).latency) then

                if (queue(back).writeAccess) then

                  dat_o <= (others=>'U');

                else

                  dat_o <= queue(back).data(cyclePosition);

                end if;

                ack_o <= '1';

                latencyCounter := latencyCounter + 1;

              else

                dat_o <= (others=>'U');

                ack_o <= '0';

                latencyCounter := 0;

                cyclePosition := cyclePosition + 1;

                if (cyclePosition = queue(back).length) then

                  back := QueueIndexInc(back);

                  cyclePosition := 0;

                end if;

              end if;

            end if;

          else

            TestError("Unexpected access.");

          end if;

        else

          if (cyclePosition /= 0) or (latencyCounter /= 0) then

            TestError("Cycle unexpectedly aborted.");

            cyclePosition := 0;

            latencyCounter := 0;

          end if;

          TestCompare(stb_i, '0', "stb_i");

        end if;

        if (front = back) then

          messageEmpty_o <= '1';

        else

          messageEmpty_o <= '0';

        end if;

      elsif (messageWrite_i'event) then

        queue(front) := message_i;

        front := QueueIndexInc(front);

        messageEmpty_o <= '0';

        messageAck_o <= '1';

        wait until messageWrite_i = '0';

        messageAck_o <= '0';

      end if;

    end loop;

  end process;

end architecture;

-------------------------------------------------------------------------------