| Line 7... |
Line 7... |
--
|
--
|
-- Description
|
-- Description
|
-- Contains a platform to build endpoints on.
|
-- Contains a platform to build endpoints on.
|
--
|
--
|
-- To Do:
|
-- To Do:
|
|
-- - Fix bug with one extra write in inbound direction.
|
|
-- - Rewrite to decrease resource usage.
|
-- - Clean up and increase the speed of the interface to packet handlers.
|
-- - Clean up and increase the speed of the interface to packet handlers.
|
-- - 8-bit deviceId has not been verified, fix.
|
-- - 8-bit deviceId has not been verified, fix.
|
-- - Egress; Place packets in different queues depending on the packet priority?
|
-- - Egress; Place packets in different queues depending on the packet priority?
|
-- - Add verification of all sizes of packets.
|
-- - Add verification of all sizes of packets.
|
--
|
--
|
| Line 42... |
Line 44... |
-- Public License along with this source; if not, download it
|
-- Public License along with this source; if not, download it
|
-- from http://www.opencores.org/lgpl.shtml
|
-- from http://www.opencores.org/lgpl.shtml
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioLogicalCommon.
|
-- RioLogicalCommon.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Ingress:
|
-- Ingress:
|
-- * Removes in-the-middle and trailing CRC.
|
-- * Removes in-the-middle and trailing CRC.
|
| Line 64... |
Line 67... |
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- Entity for RioLogicalCommon.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalCommon is
|
entity RioLogicalCommon is
|
generic(
|
generic(
|
PORTS : natural);
|
PORTS : natural);
|
port(
|
port(
|
| Line 100... |
Line 103... |
outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
|
outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- Architecture for RioLogicalCommon.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture RioLogicalCommon of RioLogicalCommon is
|
architecture RioLogicalCommon of RioLogicalCommon is
|
|
|
component RioLogicalCommonInterconnect is
|
component RioLogicalCommonInterconnect is
|
generic(
|
generic(
|
| Line 211... |
Line 214... |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Entity for RioLogicalCommonIngress.
|
-- Entity for RioLogicalCommonIngress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalCommonIngress is
|
entity RioLogicalCommonIngress is
|
port(
|
port(
|
| Line 234... |
Line 238... |
inboundAck_i : in std_logic);
|
inboundAck_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- Architecture for RioLogicalCommonIngress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture RioLogicalCommonIngress of RioLogicalCommonIngress is
|
architecture RioLogicalCommonIngress of RioLogicalCommonIngress is
|
type StateType is (IDLE,
|
type StateType is (IDLE,
|
WAIT_HEADER_0, HEADER_0, HEADER_1,
|
WAIT_HEADER_0, HEADER_0, HEADER_1,
|
SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,
|
SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,
|
| Line 464... |
Line 468... |
end process;
|
end process;
|
|
|
end architecture;
|
end architecture;
|
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- RioLogicalCommonEgress.
|
-- RioLogicalCommonEgress.
|
-- Only 8-bit and 16-bit deviceId are supported. The first write must contain
|
-- Only 8-bit and 16-bit deviceId are supported. The first write must contain
|
-- the 16-bit header, the second write must contain the destination address and
|
-- the 16-bit header, the second write must contain the destination address and
|
-- the third must contain the source address.
|
-- the third must contain the source address.
|
| Line 477... |
Line 482... |
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Entity for RioLogicalCommonEgress.
|
-- Entity for RioLogicalCommonEgress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalCommonEgress is
|
entity RioLogicalCommonEgress is
|
port(
|
port(
|
| Line 732... |
Line 738... |
|
|
when CRC_LAST =>
|
when CRC_LAST =>
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
--
|
--
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
if (packetPosition < 19) then
|
if (packetPosition <= 19) then
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContent <= '1';
|
writeContent <= '1';
|
writeContentData1 <= crc16Current & x"0000";
|
writeContentData1 <= crc16Current & x"0000";
|
end if;
|
end if;
|
elsif (packetPosition = 19) then
|
|
if (tt = "01") then
|
|
|
|
end if;
|
|
else
|
else
|
if (tt = "01") then
|
if (tt = "01") then
|
writeContent <= '1';
|
writeContent <= '1';
|
writeContentData1 <= writeContentData2(31 downto 16) & crc16Temp;
|
writeContentData1 <= writeContentData2(31 downto 16) & crc16Temp;
|
packetPosition <= packetPosition + 1;
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
state <= SEND_FRAME;
|
state <= SEND_FRAME;
|
|
|
| Line 796... |
Line 797... |
end architecture;
|
end architecture;
|
|
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- RioLogicalCommonIngress.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
use work.rio_common.all;
|
use work.rio_common.all;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- Entity for RioLogicalCommonInterconnect.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
entity RioLogicalCommonInterconnect is
|
entity RioLogicalCommonInterconnect is
|
generic(
|
generic(
|
WIDTH : natural);
|
WIDTH : natural);
|
port(
|
port(
|
| Line 826... |
Line 826... |
ack_i : in std_logic);
|
ack_i : in std_logic);
|
end entity;
|
end entity;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
-- Architecture for RioLogicalCommonInterconnect.
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture RioLogicalCommonInterconnectImpl of RioLogicalCommonInterconnect is
|
architecture RioLogicalCommonInterconnectImpl of RioLogicalCommonInterconnect is
|
signal activeCycle : std_logic;
|
signal activeCycle : std_logic;
|
signal selectedMaster : natural range 0 to WIDTH-1;
|
signal selectedMaster : natural range 0 to WIDTH-1;
|
begin
|
begin
|
