OpenCores
URL https://opencores.org/ocsvn/risc16f84/risc16f84/trunk

Subversion Repositories risc16f84

[/] [risc16f84/] [trunk/] [risc16f84_clk2x.v] - Diff between revs 7 and 10

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 7 Rev 10
Line 152... Line 152...
//                  by the new signals "c_subtract_zero" and "c_dig_subtract_zero"
//                  by the new signals "c_subtract_zero" and "c_dig_subtract_zero"
// Update: 10/24/05 Added code patches to fix interrupt bug and status flag updates
// Update: 10/24/05 Added code patches to fix interrupt bug and status flag updates
//                  when using literal value of 0x03.  These bugs were reported by
//                  when using literal value of 0x03.  These bugs were reported by
//                  an opencores.org user.  Added three "disable_status_x" signals.
//                  an opencores.org user.  Added three "disable_status_x" signals.
//                  Modified file still needs to be tested.
//                  Modified file still needs to be tested.
 
// Update: 06/29/13 This project is now CC-BY licensed.  See risc16f84_license.txt
 
//                  for details.
//
//
// Description
// Description
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// This logic module implements a small RISC microcontroller, with functions
// This logic module implements a small RISC microcontroller, with functions
// and instruction set very similar to those of the Microchip 16F84 chip.
// and instruction set very similar to those of the Microchip 16F84 chip.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.