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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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package pkg_xilinx_prims is
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attribute INIT : string;
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attribute INIT_00 : string;
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attribute INIT_01 : string;
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attribute INIT_02 : string;
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attribute INIT_03 : string;
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attribute INIT_04 : string;
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attribute INIT_05 : string;
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attribute INIT_06 : string;
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attribute INIT_07 : string;
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attribute INIT_08 : string;
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attribute INIT_09 : string;
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attribute INIT_0A : string;
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attribute INIT_0B : string;
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attribute INIT_0C : string;
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attribute INIT_0D : string;
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attribute INIT_0E : string;
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attribute INIT_0F : string;
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attribute RLOC : string;
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attribute HU_SET : string;
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function str2slv (str : string) return std_logic_vector;
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component fd port (
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d : in std_logic; c : in std_logic; q : out std_logic );
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end component;
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component fde port (
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d : in std_logic; c : in std_logic; ce : in std_logic; q : out std_logic );
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end component;
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component fdc port (
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d : in std_logic; c : in std_logic; clr : in std_logic; q : out std_logic );
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end component;
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component fdce port (
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d : in std_logic; c : in std_logic; clr : in std_logic; ce : in std_logic;
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q : out std_logic );
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end component;
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component fdpe port(
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d : in std_logic; c : in std_logic; pre : in std_logic; ce : in std_logic;
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q : out std_logic );
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end component;
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component ram16x1d
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port (
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a0, a1, a2, a3 : in std_logic;
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dpra0, dpra1, dpra2, dpra3 : in std_logic;
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wclk : in std_logic;
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we : in std_logic;
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d : in std_logic;
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spo : out std_logic;
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dpo : out std_logic
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);
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end component;
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component lut4
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--pragma translate_off
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generic (
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INIT : std_logic_vector (15 downto 0)
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);
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--pragma translate_on
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port (
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i0 : in std_logic;
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i1 : in std_logic;
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i2 : in std_logic;
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i3 : in std_logic;
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O : out std_logic
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);
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end component;
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component mult_and
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port (
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i0 : in std_logic;
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i1 : in std_logic;
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lo : out std_logic
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);
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end component;
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component muxcy
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port (
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di : in std_logic;
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ci : in std_logic;
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s : in std_logic;
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o : out std_logic
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);
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end component;
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component xorcy
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port (
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li : in std_logic;
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ci : in std_logic;
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o : out std_logic
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);
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end component;
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component muxf6
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port (
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o : OUT std_logic;
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i0 : IN std_logic;
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i1 : IN std_logic;
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s : IN std_logic
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);
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end component;
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component muxf5
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port (
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o : OUT std_logic;
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i0 : IN std_logic;
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i1 : IN std_logic;
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s : IN std_logic
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);
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end component;
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component ramb4_s2_s2
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--pragma translate_off
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generic (
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INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
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INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
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);
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--pragma translate_on
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port (
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dob : out std_logic_vector (1 downto 0);
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dib : in std_logic_vector (1 downto 0);
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addrb : in std_logic_vector (10 downto 0);
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web : in std_logic;
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enb : in std_logic;
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rstb : in std_logic;
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clkb : in std_logic;
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doa : out std_logic_vector (1 downto 0);
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dia : in std_logic_vector (1 downto 0);
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addra : in std_logic_vector (10 downto 0);
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wea : in std_logic;
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ena : in std_logic;
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rsta : in std_logic;
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clka : in std_logic
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);
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end component;
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end;
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package body pkg_xilinx_prims is
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function str2slv (str : string) return std_logic_vector is
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variable result : std_logic_vector (str'length*4-1 downto 0);
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begin
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for i in 0 to str'length-1 loop
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case str(str'high-i) is
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when '0' => result(i*4+3 downto i*4) := x"0";
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when '1' => result(i*4+3 downto i*4) := x"1";
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when '2' => result(i*4+3 downto i*4) := x"2";
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when '3' => result(i*4+3 downto i*4) := x"3";
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when '4' => result(i*4+3 downto i*4) := x"4";
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when '5' => result(i*4+3 downto i*4) := x"5";
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when '6' => result(i*4+3 downto i*4) := x"6";
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when '7' => result(i*4+3 downto i*4) := x"7";
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when '8' => result(i*4+3 downto i*4) := x"8";
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when '9' => result(i*4+3 downto i*4) := x"9";
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when 'a' | 'A' => result(i*4+3 downto i*4) := x"A";
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when 'b' | 'B' => result(i*4+3 downto i*4) := x"B";
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when 'c' | 'C' => result(i*4+3 downto i*4) := x"C";
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when 'd' | 'D' => result(i*4+3 downto i*4) := x"D";
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when 'e' | 'E' => result(i*4+3 downto i*4) := x"E";
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when 'f' | 'F' => result(i*4+3 downto i*4) := x"F";
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when others => result(i*4+3 downto i*4) := "XXXX";
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end case;
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end loop;
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return result;
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end str2slv;
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end;
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