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--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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use work.pkg_risc5x.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity REGS is
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port (
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WE : in std_logic;
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RE : in std_logic;
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BANK : in std_logic_vector(1 downto 0);
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LOCATION : in std_logic_vector(4 downto 0);
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DIN : in std_logic_vector(7 downto 0);
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DOUT : out std_logic_vector(7 downto 0);
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RESET : in std_logic;
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CLK : in std_logic
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);
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end;
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--
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-- USE THIS ARCHITECTURE FOR XILINX
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--
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use work.pkg_risc5x.all;
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use work.pkg_xilinx_prims.all;
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use work.pkg_prims.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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architecture VIRTEX of REGS is
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constant WIDTH : natural := 8;
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constant OP_REG : boolean := false;
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type slv_array is array (natural range <>) of std_logic_vector(WIDTH-1 downto 0);
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signal ram_out : slv_array(4 downto 0);
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signal wen_int : std_logic_vector(4 downto 0);
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signal sel : std_logic_vector(2 downto 0);
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begin -- architecture
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-- ram mapping
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-- bank location
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-- xx 00xxx special registers
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-- xx 01xxx common 8 to all banks
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-- 00 1xxxx 16 bank 0
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-- 01 1xxxx 16 bank 1
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-- 10 1xxxx 16 bank 2
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-- 11 1xxxx 16 bank 3
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p_wen_comb : process (BANK,LOCATION,WE)
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variable addr : std_logic_vector(3 downto 0);
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begin
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addr := (BANK & LOCATION(4 downto 3));
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wen_int <= (others => '0');
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case addr(3 downto 1) is
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when "001" => wen_int(0) <= WE; -- bank0
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when "011" => wen_int(1) <= WE; -- bank1
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when "101" => wen_int(2) <= WE; -- bank2
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when "111" => wen_int(3) <= WE; -- bank3
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when others => null;
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end case;
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if (LOCATION(4 downto 3) = "01") then
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wen_int(4) <= WE; -- common
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end if;
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end process;
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ram_bit : for i in 0 to WIDTH-1 generate
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begin
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rams : for j in 0 to 4 generate
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attribute RLOC of ram: label is "R" & integer'image((WIDTH -1)-i) & "C" & integer'image((j+1)/2) & ".S" & integer'image(1 - ((j+1) mod 2));
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begin
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ram : RAM16X1D
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port map (
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a0 => LOCATION(0),
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a1 => LOCATION(1),
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a2 => LOCATION(2),
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a3 => LOCATION(3),
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dpra0 => LOCATION(0),
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dpra1 => LOCATION(1),
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dpra2 => LOCATION(2),
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dpra3 => LOCATION(3),
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wclk => CLK,
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we => wen_int(j),
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d => DIN(i),
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dpo => ram_out(j)(i));
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end generate;
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end generate;
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SEL <= BANK & LOCATION(4);
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mux : if true generate
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attribute RLOC of mux8_1: label is "R0C3";
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begin
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mux8_1 : MUX8
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generic map (
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WIDTH => WIDTH,
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OP_REG => OP_REG
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)
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port map (
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DIN7 => ram_out(3),
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DIN6 => ram_out(4),
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DIN5 => ram_out(2),
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DIN4 => ram_out(4),
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DIN3 => ram_out(1),
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DIN2 => ram_out(4),
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DIN1 => ram_out(0),
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DIN0 => ram_out(4),
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SEL => sel,
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ENA => '1', -- not used
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CLK => CLK, -- not used
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DOUT => DOUT
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);
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end generate;
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end VIRTEX;
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--pragma translate_off
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use work.pkg_risc5x.all;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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architecture RTL of REGS is
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signal final_addr : std_logic_vector(6 downto 0);
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constant WIDTH : natural := 8;
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constant OP_REG : boolean := false;
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-- following required for simulation model only
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constant nwords : integer := 2 ** 7;
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type ram_type is array (0 to nwords-1) of std_logic_vector(WIDTH-1 downto 0);
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signal ram_read_data : std_logic_vector(WIDTH-1 downto 0);
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--shared variable ram :ram_type := (others => (others => 'X')); -- helps debug no end!
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shared variable ram :ram_type := (others => (others => '0'));
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begin -- architecture
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p_remap : process(BANK,LOCATION)
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variable addr : std_logic_vector(3 downto 0);
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begin
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addr := (BANK & LOCATION(4 downto 3));
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final_addr <= "0000000";
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case addr is
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when "0001" => final_addr <= "0000" & LOCATION(2 downto 0);
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when "0101" => final_addr <= "0000" & LOCATION(2 downto 0);
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when "1001" => final_addr <= "0000" & LOCATION(2 downto 0);
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when "1101" => final_addr <= "0000" & LOCATION(2 downto 0);
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-- bank #0
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when "0010" => final_addr <= "0001" & LOCATION(2 downto 0);
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when "0011" => final_addr <= "0010" & LOCATION(2 downto 0);
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-- bank #1
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when "0110" => final_addr <= "0011" & LOCATION(2 downto 0);
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when "0111" => final_addr <= "0100" & LOCATION(2 downto 0);
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-- bank #2
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when "1010" => final_addr <= "0101" & LOCATION(2 downto 0);
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when "1011" => final_addr <= "0110" & LOCATION(2 downto 0);
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-- bank #3
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when "1110" => final_addr <= "0111" & LOCATION(2 downto 0);
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when "1111" => final_addr <= "1000" & LOCATION(2 downto 0);
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when others => null;
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end case;
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end process;
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-- you should replace the following simulation memory model
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-- with a dpram (no clock delay on read) for synthesis if
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-- you do not wish to use the Xilinx Virtex architecture.
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-- i.e.
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--
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--U1: dpram
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-- generic map (addr_bits => 7,
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-- data_bits => 8)
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-- port map (
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-- reset => RESET,
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-- wr_clk => CLK,
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-- wr_en => WE,
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-- wr_addr => final_addr,
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-- wr_data => DIN,
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-- rd_clk => '0',
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-- rd_addr => final_addr,
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-- rd_data => DOUT
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-- );
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-- SIMULATION MODEL OF RAM
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p_ram_write : process
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variable ram_addr : integer := 0;
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begin
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wait until CLK'event and (CLK = '1');
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if (WE = '1') then
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ram_addr := slv_to_integer(final_addr);
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ram(ram_addr) := DIN;
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end if;
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end process;
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p_ram_read_comb : process(CLK,final_addr)
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variable ram_addr : integer := 0;
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begin
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ram_addr := slv_to_integer(final_addr);
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ram_read_data <= ram(ram_addr);
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end process;
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opreg : if OP_REG generate
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p_opreg : process
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begin
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wait until CLK'event and (CLK = '1');
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if (RE = '1') then
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DOUT <= ram_read_data;
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end if;
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end process;
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end generate;
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opwire : if not OP_REG generate
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DOUT <= ram_read_data;
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end generate;
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end RTL;
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--pragma translate_on
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No newline at end of file
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No newline at end of file
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