| Line 1... |
Line 1... |
System-On-Chip template based on Rocket-chip (RISC-V ISA). VHDL implementation.
|
System-On-Chip template based on synthesisable processor compliant with the RISC-V architecture.
|
=====================
|
=====================
|
|
|
This repository provides open source System-on-Chip implementation based on
|
This repository provides open source System-on-Chip implementation based on
|
64-bits CPU "Rocket-chip" distributed under BSD license. SOC source files
|
64-bits CPU "Rocket-chip" distributed under BSD license. SOC source files
|
either include general set of peripheries, FPGA CADs projects files, own
|
either include general set of peripheries, FPGA CADs projects files, own
|
| Line 21... |
Line 21... |
at the University of California, Berkeley.
|
at the University of California, Berkeley.
|
|
|
Parameterized generator of the Rocket-chip can be found here:
|
Parameterized generator of the Rocket-chip can be found here:
|
[https://github.com/ucb-bar](https://github.com/ucb-bar)
|
[https://github.com/ucb-bar](https://github.com/ucb-bar)
|
|
|
## System-on-Chip structure and performance
|
## What is River CPU?
|
|
|
SoC documentation in [.pdf](rocket_soc/docs/riscv_soc_descr.pdf) and
|
It's my own implementation of RISC-V ISA used in a several projects including
|
[.html](http://sergeykhbr.github.io/riscv_vhdl/) formats.
|
the multi-sytem Satellite Navigation receiver. It is great for an
|
|
embedded applications with active usage of 64-bits computations (like DSP).
|
|
**River CPU** includes the following tools and features:
|
|
|
|
1. Source code
|
|
- */debugger/cpu_fnc_plugin* - Functional RISC-V CPU model.
|
|
- */debugger/cpu_sysc_plugin* - Precise SystemC RIVER CPU model.
|
|
- */rtl/riverlib* - synthesisable VHDL model of a 64-bit processor compliant with the RISC-V architecture.
|
|
2. Advanced debugging features
|
|
- Test Access Points (TAPs) via Ethernet, UART and JTAG in one system.
|
|
- System Bus tracer
|
|
- Pipeline statistic (CPI, HW stacktrace) in a real-time on HW level.
|
|
- Plug'n'Play information
|
|
3. Integration with GUI from the very beginning.
|
|
|
|
My goal is to develop open source fault-tolerant processor with the user-friendly
|
|
framework.
|
|
|
Performance analysis is based on
|
## System-on-Chip structure
|
[**Dhrystone v2.1. benchmark**](http://fossies.org/linux/privat/old/dhrystone-2.1.tar.gz/)
|
|
that is very compact and entirely ported into Zephyr shell example.
|
SoC documentation in [.pdf](docs/riscv_vhdl_trm.pdf) and
|
You can run it yourself and verify results (see below).
|
[.html](http://sergeykhbr.github.io/riscv_vhdl/) formats.
|
|
|
**RISC-V Instruction simulator** - always one instruction per clock.
|
|
**FPGA SOC based on "Rocket" CPU** - single core/single issue 64-bits CPU
|
|
with disabled L1toL2 interconnect (Verilog generated from Scala sources).
|
|
**FPGA SOC based on "River" CPU** - single core/single issue 64-bits CPU is my own
|
|
implementation of RISC-V ISA (VHDL with SystemC as reference).
|
|
|
|
|
|
Target | usec per
1 dhry | Dhrystone
per sec | MHz,
max | FPU | OS | Optim.
|
|
-------|:-------------------:|:---------------------:|:------------:|:---:|----|----
|
|
RISC-V simulator v3.1 | 12.0 | **77257.0** | - | No | Zephyr 1.3 | -O2
|
|
FPGA SoC with "Rocket" v3.1 | 28.0 | **34964.0** | 60 | No | Zephyr 1.3 | -O2
|
|
FPGA SoC with "Rocket" v4.0 | 40.7 | **24038.0** | 601 | Yes | Zephyr 1.5 | -O2
|
|
FPGA SoC with "River " v4.0 | 28.0 | **35259.0** | 601 | No | Zephyr 1.5 | -O2
|
|
RISC-V simulator v5.1 | 12.0 | **65652.0** | - | No | Zephyr 1.6 | -O0
|
|
RISC-V simulator v5.1 | 12.0 | **76719.0** | - | No | Zephyr 1.6 | -O2
|
|
FPGA SoC with "Rocket" v5.1 | 41.0 | **23999.0** | 601 | Yes | Zephyr 1.6 | -O2
|
|
FPGA SoC with "River" v5.1 | 28.0 | **35121.0** | 601 | No | Zephyr 1.6 | -O2
|
|
FPGA SoC with "LEON3" SPARC | 20.0 | **48229.0** | 60 | No | Bare metal | -O0
|
|
FPGA SoC with "LEON3" SPARC | 8.0 | **119515.0** | 60 | No | Bare metal | -O2
|
|
|
|
1 - Actual SoC frequency is 40 MHz (to meet FPU constrains) but
|
|
Dhrystone benchmark uses constant 60 MHz and high precision counter (in clock cycles)
|
|
to compute results in msec. Timer value doesn't depend of clock frequency.
|
|
You can find FPGA bit-files with Rocket and River CPUs in the repository. I am
|
|
also ready to share my framework for Leon3 SPARC V8 processor (SoC and FW) by request.
|
|
|
|
Access to all memory banks and peripheries in the same clock domain is always
|
## Performance
|
one clock in this SOC (without wait-states). So, this benchmark
|
|
|
Performance analysis is based on very compact
|
|
[**Dhrystone v2.1. benchmark**](http://fossies.org/linux/privat/old/dhrystone-2.1.tar.gz/)
|
|
application available as the bare-metal test in *$(TOP)/example/dhrystone21*
|
|
folder and entirely ported into Zephyr shell (see animated gif below). Benchmark was executed
|
|
with enabled (-O0) and disabled (-O2) optimization to define HW and GCC-compiler advantages.
|
|
All sources are available and could be run on the simulator or on the
|
|
different FPGA targets.
|
|
|
|
Target | Git tag | Dhrystone
per sec,
-O0 | Dhrystone
per sec,
-O2 | Information.
|
|
-----------------|:-------:|:------------------------------:|:------------------------------:|:------------
|
|
RISC-V simulator | v6.0 | **65652.0** | **76719.0** | Ubuntu GNU GCC 6.1.0 toolchain RV64IMA custom build
|
|
"Rocket" CPU | v6.0 | - | **23999.0** | GCC 6.1.0
|
|
"River" CPU | v6.0 | - | **35121.0** | GCC 6.1.0
|
|
RISC-V simulator | latest | **76824.0** | **176469.0** | GCC 7.1.1 with the compressed instructions set
|
|
"River" CPU | latest | **29440.0** | **69605.0** | GCC 7.1.1 with the compressed instructions set
|
|
"LEON3" SPARC V8 | No | **48229.0** | **119515.0** | sparc-elf-gcc 4.4.2 with the custom FPGA system
|
|
ARM simulator | latest | soon | soon | arm-none-eabi-gcc 7.2.0
|
|
ARM Cortex-R5 | No | soon | soon | arm-none-eabi-gcc 7.2.0 with the custom FPGA system
|
|
|
|
Access to all memory banks and peripheries for all targets (including ARM and Leon3) is made
|
|
in the same clock domain and always is
|
|
one clock(without wait-states). So, this benchmark
|
result (**Dhrystone per seconds**) shows performance of the CPU with integer
|
result (**Dhrystone per seconds**) shows performance of the CPU with integer
|
instructions and degradation of the CPI relative ideal (simulation) case.
|
instructions and degradation of the CPI relative ideal (simulation) case.
|
|
|
**In my opinion compiler affects on benchmark results much more than hardware
|
**Since the tag 'v7.0' RIVER CPU is the main processor in the system and all issues
|
architecture and there's a lot of work for RISC-V compiler developers.
|
related to Rocket-chip instance will be supported only by request.**
|
So, use as new compiler as possible.**
|
|
|
|
## Repository structure
|
## Repository structure
|
|
|
This repository consists of three sub-projects each in own subfolder:
|
This repository consists of three sub-projects each in own subfolder:
|
|
|
- **rocket_soc** is the folder with VHDL/Verilog sources of the SOC
|
- **rtl** is the folder with VHDL/Verilog sources of the SOC
|
including synthesizable processors *"Rocket"* and *"River"* and peripheries.
|
including synthesizable processors *"Rocket"* and *"River"* and peripheries.
|
Source code is portable on almost any FPGA is due to the fact that
|
Source code is portable on almost any FPGA is due to the fact that
|
technology dependant modules (like *PLL*, *IO-buffers*
|
technology dependant modules (like *PLL*, *IO-buffers*
|
etc) instantiated inside of "virtual" components
|
etc) instantiated inside of "virtual" components
|
in a similar to Gailser's *[GRLIB](www.gailser.com)* way.
|
in a similar to Gailser's *[GRLIB](www.gailser.com)* way.
|
Full SOC design without FPU occupies less than 5 % of FPGA resources (Virtex6).
|
Full SOC design without FPU occupies less than 5 % of FPGA resources (Virtex6).
|
*"Rocket-chip"* CPU itself is the modern **64-bits processor
|
*"Rocket-chip"* CPU itself is the modern **64-bits processor
|
with L1-cache, branch-predictor, MMU and virtualization support**.
|
with L1-cache, branch-predictor, MMU and virtualization support**.
|
This sub-project also contains:
|
This sub-project also contains:
|
* *fw*: directory with the bootloader and FW examples.
|
|
* *fw_images*: directory with the ROM images in HEX-format.
|
* *fw_images*: directory with the ROM images in HEX-format.
|
* *prj*: project files for different CADs (Xilinx ISE, ModelSim).
|
* *prj*: project files for different CADs (Xilinx ISE, ModelSim).
|
* *tb*: VHDL testbech of the full system and utilities.
|
* *tb*: VHDL testbech of the full system and utilities.
|
* *bit_files*: Pre-built FPGA images for ML605 and KC705 boards.
|
* *bit_files*: Pre-built FPGA images for ML605 and KC705 boards.
|
- **zephyr** is the ported on RISC-V 64-bits operation system.
|
- **examples** folder contains several C-examples that could help start working
|
|
with the RISC-V system:
|
|
* *boot* is the code of the Boot Loader. It is also used for the SRAM
|
|
initialization with the FW image and it allows to run examples on
|
|
FPGA without using the debugger and external flash memory.
|
|
* *helloworld* the simplest example with UART output.
|
|
* *isrdemo* example with 1 second interrupt from timer and debug output.
|
|
* *zephyr* is ported on RISC-V 64-bits operation system.
|
Information about this Real-Time Operation System for Internet of
|
Information about this Real-Time Operation System for Internet of
|
Things Devices provided by [Zephyr Project](https://www.zephyrproject.org/).
|
Things Devices provided by [Zephyr Project](https://www.zephyrproject.org/).
|
Early support for the Zephyr Project includes Intel Corporation,
|
Early support for the Zephyr Project includes Intel Corporation,
|
NXP Semiconductors N.V., Synopsys, Inc. and UbiquiOS Technology Limited.
|
NXP Semiconductors N.V., Synopsys, Inc. and UbiquiOS Technology Limited.
|
- **debugger**. The last piece of the ready-to-use open HW/SW system is
|
- **debugger**. The last piece of the ready-to-use open HW/SW system is
|
| Line 101... |
Line 118... |
via [Ethernet](http://sergeykhbr.github.io/riscv_vhdl/eth_link.html)
|
via [Ethernet](http://sergeykhbr.github.io/riscv_vhdl/eth_link.html)
|
using EDCL protocol over UDP. To provide this functionality SOC includes
|
using EDCL protocol over UDP. To provide this functionality SOC includes
|
[**10/100 Ethernet MAC with EDCL**](http://sergeykhbr.github.io/riscv_vhdl/eth_link.html)
|
[**10/100 Ethernet MAC with EDCL**](http://sergeykhbr.github.io/riscv_vhdl/eth_link.html)
|
and [**Debug Support Unit (DSU)**](http://sergeykhbr.github.io/riscv_vhdl/periphery_page_1.html)
|
and [**Debug Support Unit (DSU)**](http://sergeykhbr.github.io/riscv_vhdl/periphery_page_1.html)
|
devices on AMBA AXI4 bus.
|
devices on AMBA AXI4 bus.
|
- **RISC-V "River" core**. It's my own implementation of RISC-V ISA that is ideal
|
|
for embedded application with active usage of 64-bits computations
|
|
(DSP for Satellite Navigation). I've specified the following principles for myself:
|
|
1. Unified Verification Methodology (UVM)
|
|
- */debugger/cpu_fnc_plugin* - Functional RISC-V CPU model.
|
|
- */debugger/cpu_sysc_plugin* - Precise SystemC RIVER CPU model.
|
|
- */rocket_soc/riverlib* - RIVER VHDL sources with VCD-stimulus from SystemC.
|
|
2. Advanced debugging features: bus tracing, pipeline statistic (like CPI) in real-time on HW level etc.
|
|
3. Integration with GUI from the very beginning.
|
|
I hope to develop the most friendly synthesizable processor for HW and SW developers
|
|
and provide debugging tools of professional quality.
|
|
|
|
|
|
# Step I: Simple FPGA test.
|
# Step I: Simple FPGA test.
|
|
|
You can use the pre-built FPGA image (for Xilinx ML605 or KC705 board) and any serial
|
You can use the pre-built FPGA image (for Xilinx ML605 or KC705 board) and any serial
|
console application (*putty*, *screen* or other).
|
console application (*putty*, *screen* or other) to run Dhrystone v2.1 benchmark as
|
|
on the animated picture below.
|
|
|
1. Unpack and load file image *riscv_soc.bit* from */rocket_soc/bit_files/* into FPGA board.
|
|
2. Connect to serial port. I use standard console utility *screen* on Ubuntu.
|
|
|
1. Unpack and load file image *riscv_soc.bit* from */rtl/bit_files/* into FPGA board.
|
|
2. Connect to serial port. I used standard console utility *screen* on Ubuntu.
|
|
|
$ sudo apt-get install screen
|
$ sudo apt-get install screen
|
$ sudo screen /dev/ttyUSB0 115200
|
$ sudo screen /dev/ttyUSB0 115200
|
|
|
3. Use button "*Center*" to reset FPGA system and reprint initial messages:
|
3. Use button "*Center*" to reset FPGA system and reprint initial messages (or just press Enter):
|
|
|
```
|
To end the session, use *Ctrl-A*, *Shift-K*
|
Boot . . .OK
|
|
Zephyr version 1.5.0
|
|
shell>
|
|
```
|
|
|
|
Our system is ready to use. Shell command **pnp** prints SOC HW information,
|
|
command **dhry** runs Dhrystone 2.1 benchmark.
|
|
To end the session, use Ctrl-A, Shift-K
|
|
|
|
|
|
|
|
Zephyr kernel v1.6 supports shell commands from different kernel modules, to switch
|
|
one module to another use command **set_module**:
|
|
|
|
```
|
|
shell> set_module kernel
|
|
shell> version
|
|
shell> set_module soc
|
|
shell> dhry
|
|
shell> pnp
|
|
...
|
|
```
|
|
|
|
# Step II: Build and run Software models with GUI.
|
# Step II: Build and run Software models with GUI.
|
|
|
At this step we're going to build: functional models of CPU and peripheries,
|
At this step we're going to build: functional models of CPU and peripheries,
|
precise SystemC model of 'River' CPU and RISC-V Debugger with GUI
|
precise SystemC model of 'River' CPU and RISC-V Debugger with GUI
|
(MS Visual Studio project for Windows is also available).
|
(MS Visual Studio project for Windows is also available).
|
This step **doesn't require any Hardware** and the final result will look as on
|
This step **doesn't require any Hardware** and the final result will look as on
|
the following animated picture:
|
the following animated picture:
|
|
|
|
|
|
|
There's dependency of two others open source projects:
|
There's dependency of two others open source projects:
|
|
|
* **[Qt-libraries](https://www.qt.io/download/)**
|
* **[Qt-libraries](https://www.qt.io/download/)**
|
* **[SystemC library](http://accellera.org/downloads/standards/systemc)**
|
* **[SystemC library](http://accellera.org/downloads/standards/systemc)**
|
| Line 222... |
Line 208... |
|
|
# Step III: Build FPGA image
|
# Step III: Build FPGA image
|
|
|
Default VHDL configuration enables River CPU with full debug support.
|
Default VHDL configuration enables River CPU with full debug support.
|
|
|
|
|
|
|
You can enable usage of "Rocket-chip" CPU instead of "River" disabling the
|
You can enable usage of "Rocket-chip" CPU instead of "River" disabling the
|
configuration parameter in */rocket_soc/work/config_common.vhd*
|
configuration parameter in */rtl/work/config_common.vhd*
|
CFG_COMMON_RIVER_CPU_ENABLE.
|
CFG_COMMON_RIVER_CPU_ENABLE.
|
|
|
1. Open ML605 project file for Xilinx ISE14.7 *prj/ml605/riscv_soc.xise*
|
1. Open ML605 project file for Xilinx ISE14.7 *prj/ml605/riscv_soc.xise*
|
or KC705 project file for Xilinx Vivado *prj/kc705/riscv_soc.xpr*.
|
or KC705 project file for Xilinx Vivado *prj/kc705/riscv_soc.xpr*.
|
2. Edit configuration constants in file **work/config_common.vhd** if needed.
|
2. Edit configuration constants in file **work/config_common.vhd** if needed.
|
(Skip this step by default).
|
(Skip this step by default).
|
3. Use *rocket_soc/work/tb/riscv_soc_tb.vhd"* testbench file to verify
|
3. Use *rtl/work/tb/riscv_soc_tb.vhd"* testbench file to verify
|
full system including *CPU*, *UART*, *Timers*, *Ethernet*, *GPIO* etc.
|
full system including *CPU*, *UART*, *Timers*, *Ethernet*, *GPIO* etc.
|
4. Generate bit-file and load it into FPGA.
|
4. Generate bit-file and load it into FPGA.
|
|
|
|
|
# Step IV: How to build 64-bits Zephyr v1.6.0 for RISC-V or other custom firmware
|
# Step IV: How to build 64-bits Zephyr v1.6.0 for RISC-V or other custom firmware
|
| Line 250... |
Line 236... |
|
|
You can find step-by-step instruction of how to build your own
|
You can find step-by-step instruction of how to build your own
|
toolchain on [riscv.org](http://riscv.org/software-tools/). If you would like
|
toolchain on [riscv.org](http://riscv.org/software-tools/). If you would like
|
to use pre-build GCC binary files and libraries you can download it here:
|
to use pre-build GCC binary files and libraries you can download it here:
|
|
|
[Ubuntu GNU GCC 6.1.0 toolchain RV64D (207MB)](http://www.gnss-sensor.com/index.php?LinkID=1018)
|
GCC 7.1 from [SiFive](https://www.sifive.com/products/tools/) for Linux, Windows and macOS
|
[Ubuntu GNU GCC 6.1.0 toolchain RV64IMA (204MB)](http://www.gnss-sensor.com/index.php?LinkID=1017)
|
GCC 7.1 from [SysProgs](http://gnutoolchains.com/risc-v/) for Windows
|
|
|
[(obsolete) Ubuntu GNU GCC 5.1.0 toolchain RV64IMA (256MB)](http://www.gnss-sensor.com/index.php?LinkID=1013)
|
I'm on transition stage to a new v7.0 release with implemented Compressed
|
|
instructions set (C-extensions). It will allow to use the latest GCC builds without modifications.
|
|
Some fatal errors can be found during this time, sorry.
|
|
|
GCC 5.1.0 is the legacy version for *riscv_vhdl* with tag **v3.1** or older.
|
Previous obsolete GCC builds:
|
**RV64IMA** build doesn't use hardware FPU (*--soft-float*). **RV64D** build
|
|
requires FPU co-processor (*--hard-float*).
|
|
|
|
Just after you download the toolchain unpack it and set environment variable
|
* Upto release tag v6.0 was used
|
as follows:
|
[Ubuntu GNU GCC 6.1.0 toolchain RV64IMA (204MB)](http://www.gnss-sensor.com/index.php?LinkID=1017)
|
|
|
$ tar -xzvf gnu-toolchain-rv64ima.tar.gz gnu-toolchain-rv64ima
|
* Upto release tag v3.1 was used
|
$ export PATH=/home/your_path/gnu-toolchain-rv64ima/bin:$PATH
|
[Ubuntu GNU GCC 5.1.0 toolchain RV64IMA (256MB)](http://www.gnss-sensor.com/index.php?LinkID=1013)
|
|
|
If you would like to generate hex-file and use it for ROM initialization you can use
|
If you would like to generate hex-file and use it for ROM initialization you can use
|
*'elf2hex'* and *'libfesvr.so'* library from the GNU toolchain but I suggest to use my version
|
*'elf2hex'* and *'libfesvr.so'* library from the GNU toolchain but I suggest to use my version
|
of such tool *'elf2raw64'*. I've put this binary into pre-built GCC archive 'gnu_toolchain-rv64/bin'.
|
of such tool *'elf2raw64'*. I've put this binary into pre-built GCC archive 'gnu_toolchain-rv64/bin'.
|
If *elf2raw64* conflicts with installed LIBC version re-build it from *fw/elf2raw64/makefiles*
|
If *elf2raw64* conflicts with installed LIBC version re-build it from *examples/elf2raw64/makefiles*
|
directory.
|
directory.
|
|
|
## 2. Patch and build Zephyr OS v1.6.0 binary
|
## 2. Patch and build Zephyr OS v1.6.0 binary
|
|
|
$ mkdir zephyr_160
|
$ mkdir zephyr_160
|
$ cd zephyr_160
|
$ cd zephyr_160
|
$ git clone https://gerrit.zephyrproject.org/r/zephyr
|
$ git clone https://github.com/zephyrproject-rtos/zephyr.git
|
$ cd zephyr
|
$ cd zephyr
|
$ git checkout tags/v1.6.0
|
$ git checkout tags/v1.6.0
|
$ cp ../../riscv_vhdl/zephyr/v1.6.0-riscv64-base.diff .
|
$ cp ../../riscv_vhdl/zephyr/v1.6.0-riscv64-base.diff .
|
$ cp ../../riscv_vhdl/zephyr/v1.6.0-riscv64-exten.diff .
|
$ cp ../../riscv_vhdl/zephyr/v1.6.0-riscv64-exten.diff .
|
$ git apply v1.6.0-riscv64-base.diff
|
$ git apply v1.6.0-riscv64-base.diff
|
| Line 304... |
Line 290... |
|
|
-h -- specify HEX format of the output file.
|
-h -- specify HEX format of the output file.
|
-f 262144 -- specify total ROM size in bytes.
|
-f 262144 -- specify total ROM size in bytes.
|
-l 8 -- specify number of bytes in one line (AXI databus width). Default is 16.
|
-l 8 -- specify number of bytes in one line (AXI databus width). Default is 16.
|
|
|
Copy *fwimage.hex* to rocket_soc subdirectory
|
Copy *fwimage.hex* to rtl subdirectory
|
|
|
$ cp fwimage.hex ../../../rocket_soc/fw_images
|
$ cp fwimage.hex ../../../rtl/fw_images
|
|
|
## 3. Debug Zephyr kernel with debug symbols.
|
## 3. Debug Zephyr kernel with debug symbols.
|
|
|
Our debugger allows to use debug information from the elf-file as on the
|
Use the following debugger's console commands to load symbols information
|
picture bellow:
|
from elf-file:
|
|
|
|
|
|
|
To achieve such results just use the console command *'loadelf'*:
|
|
|
|
riscv# loadelf zephyr.elf
|
riscv# loadelf zephyr.elf
|
riscv# loadelf zephyr.elf nocode
|
riscv# loadelf zephyr.elf nocode
|
|
|
The second command loads debug information without target reprogramming.
|
The second command loads debug information without target reprogramming.
|
|
|
## 4. Build and run custom FW like 'Hello World' example.
|
## 4. Build and run custom FW like 'Hello World' example.
|
|
|
Build example:
|
Build example:
|
|
|
$ cd /your_git_path/rocket_soc/fw/helloworld/makefiles
|
$ cd /your_git_path/examples/helloworld/makefiles
|
$ make
|
$ make
|
|
|
Run Risc-V Debugger application:
|
Run Risc-V Debugger application:
|
|
|
$ ./your_git_path/debugger/linuxbuild/bin/_run_functional_sim.sh
|
$ ./your_git_path/debugger/linuxbuild/bin/_run_functional_sim.sh
|
| Line 360... |
Line 342... |
so if you'd like to repeat test reload image using **loadelf** command.
|
so if you'd like to repeat test reload image using **loadelf** command.
|
|
|
Now we can also generate HEX-file for ROM initialization to do that
|
Now we can also generate HEX-file for ROM initialization to do that
|
see other example with **bootrom** implementation
|
see other example with **bootrom** implementation
|
|
|
$ cd rocket_soc/fw/boot/makefiles
|
$ cd examples/boot/makefiles
|
$ make
|
$ make
|
$ cd ../linuxbuild/bin
|
$ cd ../linuxbuild/bin
|
|
|
Opened directory contains the following files:
|
Opened directory contains the following files:
|
- _bootimage_ - elf-file (not used by SOC).
|
- _bootimage_ - elf-file (not used by SOC).
|
| Line 379... |
Line 361... |
|
|
My usual FPGA setup is ML605 board and debugger that is running on Windows 7
|
My usual FPGA setup is ML605 board and debugger that is running on Windows 7
|
from Visual Studio project, so other target configurations (linux + KC705)
|
from Visual Studio project, so other target configurations (linux + KC705)
|
could contain errors that are fixing with a small delay. Let me know if see one.
|
could contain errors that are fixing with a small delay. Let me know if see one.
|
|
|
|
## 5. Example of debug session with RF front-end and GNSS IPs on ML605 board.
|
|
|
|
|
|
|
|
|
## Versions History
|
## Versions History
|
|
|
|
### Implemented functionality (v6.0)
|
|
|
|
- GNSS IPs successfully integrated into RISC-V based SoC.
|
|
- Add Test Access (TAP) over Serial port.
|
|
- Add GUI integration with Open Street Maps and position tracking.
|
|
- Add performance analisys tool into GUI.
|
|
|
### Implemented functionality (v5.1)
|
### Implemented functionality (v5.1)
|
|
|
- "RIVER" critical bugs fixed:Not decoded SRAI instrucion, missed exception generation.
|
- "RIVER" critical bugs fixed:Not decoded SRAI instrucion, missed exception generation.
|
- Zephyr v1.6.0 ported with *unikernel* instead of the obsolete *nanokernel*.
|
- Zephyr v1.6.0 ported with *unikernel* instead of the obsolete *nanokernel*.
|
|
|
