URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [msvc13/] [libdbg64g/] [exportmap.def] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 12...	Line 12...
`RISCV_trigger_hap`	`RISCV_trigger_hap`
`RISCV_get_class`	`RISCV_get_class`
`RISCV_create_service`	`RISCV_create_service`
`RISCV_get_service`	`RISCV_get_service`
`RISCV_get_service_iface`	`RISCV_get_service_iface`
	`RISCV_get_service_port_iface`
`RISCV_generate_name`	`RISCV_generate_name`
`RISCV_add_default_output`	`RISCV_add_default_output`
`RISCV_remove_default_output`	`RISCV_remove_default_output`
`RISCV_sprintf`	`RISCV_sprintf`
`RISCV_printf`	`RISCV_printf`
`RISCV_print_bin`	`RISCV_print_bin`
`RISCV_sleep_ms`	`RISCV_sleep_ms`
`RISCV_get_time_ms`	`RISCV_get_time_ms`
`RISCV_get_pid`	`RISCV_get_pid`
	`RISCV_memory_barrier`
`RISCV_thread_create`	`RISCV_thread_create`
`RISCV_thread_id`	`RISCV_thread_id`
`RISCV_thread_join`	`RISCV_thread_join`
`RISCV_mutex_init`	`RISCV_mutex_init`
`RISCV_mutex_lock`	`RISCV_mutex_lock`
Line 35...	Line 37...
`RISCV_event_set`	`RISCV_event_set`
`RISCV_event_is_set`	`RISCV_event_is_set`
`RISCV_event_clear`	`RISCV_event_clear`
`RISCV_event_wait`	`RISCV_event_wait`
`RISCV_event_wait_ms`	`RISCV_event_wait_ms`
	`RISCV_memshare_create`
	`RISCV_memshare_map`
	`RISCV_memshare_unmap`
	`RISCV_memshare_delete`
`RISCV_get_core_folder`	`RISCV_get_core_folder`
`RISCV_set_current_dir`	`RISCV_set_current_dir`
`RISCV_get_services_with_iface`	`RISCV_get_services_with_iface`
`RISCV_get_clock_services`	`RISCV_get_clock_services`
`RISCV_break_simulation`	`RISCV_break_simulation`