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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [isocinfo.h] - Diff between revs 3 and 4

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Line 3... Line 3...
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
 * @brief      SOC Information interface.
 * @brief      SOC Information interface.
 */
 */
 
 
#ifndef __DEBUGGER_ISOCINFO_H__
#ifndef __DEBUGGER_COMMON_CORESERVICES_ISOCINFO_H__
#define __DEBUGGER_ISOCINFO_H__
#define __DEBUGGER_COMMON_CORESERVICES_ISOCINFO_H__
 
 
#include "iface.h"
#include <iface.h>
#include "attribute.h"
#include <attribute.h>
 
#include "debug/debugmap.h"
 
 
namespace debugger {
namespace debugger {
 
 
static const char *IFACE_SOC_INFO = "ISocInfo";
static const char *IFACE_SOC_INFO = "ISocInfo";
 
 
static const int CFG_NASTI_MASTER_CACHED    = 0;
static const int CFG_NASTI_MASTER_CACHED    = 0;
static const int CFG_NASTI_MASTER_UNCACHED  = 1;
static const int CFG_NASTI_MASTER_UNCACHED  = 1;
static const int CFG_NASTI_MASTER_ETHMAC    = 2;
static const int CFG_NASTI_MASTER_ETHMAC    = 2;
static const int CFG_NASTI_MASTER_TOTAL     = 3;
static const int CFG_NASTI_MASTER_MSTUART   = 3;
 
static const int CFG_NASTI_MASTER_TOTAL     = 4;
 
 
static const uint16_t MST_DID_EMPTY            = 0x7755;
static const uint16_t MST_DID_EMPTY            = 0x7755;
static const uint16_t SLV_DID_EMPTY            = 0x5577;
static const uint16_t SLV_DID_EMPTY            = 0x5577;
 
 
static const uint16_t VENDOR_GNSSSENSOR        = 0x00F1;
static const uint16_t VENDOR_GNSSSENSOR        = 0x00F1;
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static const uint16_t RISCV_CACHED_TILELINK    = 0x0500;
static const uint16_t RISCV_CACHED_TILELINK    = 0x0500;
static const uint16_t RISCV_UNCACHED_TILELINK  = 0x0501;
static const uint16_t RISCV_UNCACHED_TILELINK  = 0x0501;
static const uint16_t GAISLER_ETH_MAC_MASTER   = 0x0502;
static const uint16_t GAISLER_ETH_MAC_MASTER   = 0x0502;
static const uint16_t GAISLER_ETH_EDCL_MASTER  = 0x0503;
static const uint16_t GAISLER_ETH_EDCL_MASTER  = 0x0503;
static const uint16_t RISCV_RIVER_CPU          = 0x0505;
static const uint16_t RISCV_RIVER_CPU          = 0x0505;
 
static const uint16_t GNSSSENSOR_UART_TAP      = 0x050A;
 
 
// Slaves IDs
// Slaves IDs
static const uint16_t GNSSSENSOR_ENGINE_STUB   = 0x0068;
static const uint16_t GNSSSENSOR_ENGINE_STUB   = 0x0068;
static const uint16_t GNSSSENSOR_FSE_V2_GPS    = 0x0069;
static const uint16_t GNSSSENSOR_FSE_V2_GPS    = 0x0069;
static const uint16_t GNSSSENSOR_FSE_V2_GLO    = 0x006a;
static const uint16_t GNSSSENSOR_FSE_V2_GLO    = 0x006a;
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        } bits;
        } bits;
        uint32_t val;
        uint32_t val;
    } tech;                     /// 0xfffff008: RO: technology index
    } tech;                     /// 0xfffff008: RO: technology index
    uint32_t rsrv1;             /// 0xfffff00c: 
    uint32_t rsrv1;             /// 0xfffff00c: 
    uint64_t idt;               /// 0xfffff010: 
    uint64_t idt;               /// 0xfffff010: 
    uint64_t malloc_addr;       /// 0xfffff018: RW: debuggind memalloc pointer 0x18
    uint64_t malloc_addr;       /// 0xfffff018: RW: memalloc pointer 0x18
    uint64_t malloc_size;       /// 0xfffff020: RW: debugging memalloc size 0x20
    uint64_t malloc_size;       /// 0xfffff020: RW: memalloc size 0x20
    uint64_t fwdbg1;            /// 0xfffff028: RW: FW debug register
    uint64_t fwdbg1;            /// 0xfffff028: RW: FW debug register
    uint64_t rsrv[2];           /// 0xfffff030, 0xfffff038
    uint64_t rsrv[2];           /// 0xfffff030, 0xfffff038
    uint8_t cfg_table[(1 << 12) - 0x40];/// 0xfffff040: RO: PNP configuration
    uint8_t cfg_table[(1 << 12) - 0x40];/// 0xfffff040: RO: PNP configuration
} PnpMapType;
} PnpMapType;
 
 
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    // Base Address + 0x08000 (Region 1)
    // Base Address + 0x08000 (Region 1)
    union ureg_type {
    union ureg_type {
        uint8_t buf[1 << (12 + 3)];
        uint8_t buf[1 << (12 + 3)];
        struct regs_type {
        struct regs_type {
            uint64_t iregs[32];     // integer registers
            uint64_t iregs[32];     // integer registers
            uint64_t pc;            // index = 32
            uint64_t pc;
            uint64_t npc;           // index = 33
            uint64_t npc;
            uint64_t stack_trace_cnt; // index 34
            uint64_t stack_trace_cnt; // index 34
            uint64_t rsrv1[128 - 35];
            uint64_t rsrv1[128 - 35];
            uint64_t stack_trace_buf[1];
            uint64_t stack_trace_buf[1];
            uint64_t rsrv2[128 - 1];
            uint64_t rsrv2[128 - 1];
            uint64_t instr_buf[4];  // index 256..259: Bits[63:0] (addr,instr)
            uint64_t instr_buf[4];      // Bits[63:0] (addr,instr)
            uint64_t dbg1[4];
            uint64_t dbg1[4];
        } v;
        } v;
    } ureg;
    } ureg;
    // Base Address + 0x10000 (Region 2)
    // Base Address + 0x10000 (Region 2)
    union udbg_type {
    union udbg_type {
        uint8_t buf[1 << (12 + 3)];
        uint8_t buf[1 << (12 + 3)];
        struct debug_region_type {
        struct debug_region_type {
            union control_reg {
            GenericCpuControlType control;
                uint64_t val;
 
                struct {
 
                    uint64_t halt     : 1;
 
                    uint64_t stepping : 1;
 
                    uint64_t breakpoint : 1;
 
                    uint64_t rsv1     : 1;
 
                    uint64_t core_id  : 16;
 
                    uint64_t rsv2     : 12;
 
                    uint64_t istate   : 2;  // [33:32] icache state
 
                    uint64_t rsv3     : 2;  // [35:34] 
 
                    uint64_t dstate   : 2;  // [37:36] dcache state
 
                    uint64_t rsv4     : 2;  // [39:38]
 
                    uint64_t cstate   : 2;  // [41:40] cachetop state
 
                    uint64_t rsv5     : 22;
 
                } bits;
 
            } control;
 
            uint64_t stepping_mode_steps;
            uint64_t stepping_mode_steps;
            uint64_t clock_cnt;
            uint64_t clock_cnt;
            uint64_t executed_cnt;
            uint64_t executed_cnt;
            union breakpoint_control_reg {
            union breakpoint_control_reg {
                uint64_t val;
                uint64_t val;
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};
};
 
 
 
 
const uint64_t REG_ADDR_ERROR = 0xFFFFFFFFFFFFFFFFull;
const uint64_t REG_ADDR_ERROR = 0xFFFFFFFFFFFFFFFFull;
 
 
 
#define DSUREG(x) (reinterpret_cast<uint64_t>(& \
 
        (reinterpret_cast<DsuMapType*>(0))->x))
 
 
class ISocInfo : public IFace {
class ISocInfo : public IFace {
public:
public:
    ISocInfo() : IFace(IFACE_SOC_INFO) {}
    ISocInfo() : IFace(IFACE_SOC_INFO) {}
 
 
    virtual unsigned getMastersTotal() =0;
 
    virtual unsigned getSlavesTotal() =0;
 
    virtual unsigned getRegsTotal() =0;
    virtual unsigned getRegsTotal() =0;
    virtual void getRegsList(AttributeType *lst) =0;
    virtual void getRegsList(AttributeType *lst) =0;
    virtual unsigned getCsrTotal() =0;
 
    virtual void getCsrList(AttributeType *lst) =0;
 
    virtual uint64_t csr2addr(const char *name) =0;
 
    virtual uint64_t reg2addr(const char *name) =0;
    virtual uint64_t reg2addr(const char *name) =0;
 
 
    virtual DsuMapType *getpDsu() =0;
    virtual DsuMapType *getpDsu() =0;
 
 
    virtual uint64_t addressPlugAndPlay() =0;
 
    virtual uint64_t addressGpio() =0;
 
};
};
 
 
}  // namespace debugger
}  // namespace debugger
 
 
#endif  // __DEBUGGER_ISOCINFO_H__
#endif  // __DEBUGGER_COMMON_CORESERVICES_ISOCINFO_H__
 
 
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