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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief RISC-V ISA specified structures and constants.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#ifndef __DEBUGGER_RISCV_ISA_H__
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#ifndef __DEBUGGER_RISCV_ISA_H__
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#define __DEBUGGER_RISCV_ISA_H__
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#define __DEBUGGER_RISCV_ISA_H__
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#include <inttypes.h>
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#include <inttypes.h>
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uint32_t imm20 : 1; // [31]
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uint32_t imm20 : 1; // [31]
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} bits;
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} bits;
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uint32_t value;
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uint32_t value;
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};
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};
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static const uint64_t EXT_SIGN_8 = 0xFFFFFFFFFFFFFF00LL;
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/**
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* Compressed extension types:
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*/
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// Regsiter
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union ISA_CR_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rs2 : 5; // [6:2]
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uint16_t rdrs1 : 5; // [11:7]
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uint16_t funct4 : 4; // [15:12]
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} bits;
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uint16_t value;
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};
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// Immediate
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union ISA_CI_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t imm : 5; // [6:2]
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uint16_t rdrs : 5; // [11:7]
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uint16_t imm6 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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struct sp_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t imm5 : 1; // [2]
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uint16_t imm8_7 : 2; // [4:3]
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uint16_t imm6 : 1; // [5]
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uint16_t imm4 : 1; // [6]
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uint16_t sp : 5; // [11:7]
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uint16_t imm9 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} spbits;
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struct ldsp_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t off8_6 : 3; // [4:2]
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uint16_t off4_3 : 2; // [6:5]
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uint16_t rd : 5; // [11:7]
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uint16_t off5 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} ldspbits;
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struct lwsp_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t off7_6 : 2; // [3:2]
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uint16_t off4_2 : 3; // [6:4]
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uint16_t rd : 5; // [11:7]
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uint16_t off5 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} lwspbits;
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uint16_t value;
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};
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// Stack relative Store
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union ISA_CSS_type {
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struct w_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rs2 : 5; // [6:2]
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uint16_t imm7_6 : 2; // [8:7]
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uint16_t imm5_2 : 4; // [12:9]
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uint16_t funct3 : 3; // [15:13]
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} wbits;
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struct d_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rs2 : 5; // [6:2]
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uint16_t imm8_6 : 3; // [9:7]
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uint16_t imm5_3 : 3; // [12:10]
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uint16_t funct3 : 3; // [15:13]
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} dbits;
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uint16_t value;
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};
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// Wide immediate
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union ISA_CIW_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rd : 3; // [4:2]
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uint16_t imm3 : 1; // [5]
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uint16_t imm2 : 1; // [6]
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uint16_t imm9_6 : 4; // [10:7]
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uint16_t imm5_4 : 2; // [12:11]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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uint16_t value;
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};
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// Load
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union ISA_CL_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rd : 3; // [4:2]
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uint16_t imm6 : 1; // [5]
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uint16_t imm27 : 1; // [6]
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uint16_t rs1 : 3; // [9:7]
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uint16_t imm5_3 : 3; // [12:10]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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uint16_t value;
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};
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// Store
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union ISA_CS_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t rs2 : 3; // [4:2]
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uint16_t imm6 : 1; // [5]
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uint16_t imm27 : 1; // [6]
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uint16_t rs1 : 3; // [9:7]
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uint16_t imm5_3 : 3; // [12:10]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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uint16_t value;
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};
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// Branch
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union ISA_CB_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t off5 : 1; // [2]
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uint16_t off2_1 : 2; // [4:3]
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uint16_t off7_6 : 2; // [6:5]
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uint16_t rs1 : 3; // [9:7]
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uint16_t off4_3 : 2; // [11:10]
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uint16_t off8 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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struct sh_bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t shamt : 5; // [6:2]
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uint16_t rd : 3; // [9:7]
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uint16_t funct2 : 2; // [11:10]
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uint16_t shamt5 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} shbits;
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uint16_t value;
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};
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// Jump
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union ISA_CJ_type {
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struct bits_type {
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uint16_t opcode : 2; // [1:0]
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uint16_t off5 : 1; // [2]
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uint16_t off3_1 : 3; // [5:3]
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uint16_t off7 : 1; // [6]
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uint16_t off6 : 1; // [7]
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uint16_t off10 : 1; // [8]
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uint16_t off9_8 : 2; // [10:9]
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uint16_t off4 : 1; // [11]
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uint16_t off11 : 1; // [12]
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uint16_t funct3 : 3; // [15:13]
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} bits;
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uint16_t value;
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};
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static const uint64_t EXT_SIGN_5 = 0xFFFFFFFFFFFFFFF0LL;
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static const uint64_t EXT_SIGN_6 = 0xFFFFFFFFFFFFFFE0LL;
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static const uint64_t EXT_SIGN_8 = 0xFFFFFFFFFFFFFF80LL;
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static const uint64_t EXT_SIGN_9 = 0xFFFFFFFFFFFFFF00LL;
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static const uint64_t EXT_SIGN_11 = 0xFFFFFFFFFFFFF800LL;
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static const uint64_t EXT_SIGN_12 = 0xFFFFFFFFFFFFF000LL;
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static const uint64_t EXT_SIGN_12 = 0xFFFFFFFFFFFFF000LL;
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static const uint64_t EXT_SIGN_16 = 0xFFFFFFFFFFFF0000LL;
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static const uint64_t EXT_SIGN_16 = 0xFFFFFFFFFFFF0000LL;
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static const uint64_t EXT_SIGN_32 = 0xFFFFFFFF00000000LL;
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static const uint64_t EXT_SIGN_32 = 0xFFFFFFFF00000000LL;
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static const char *const IREGS_NAMES[] = {
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static const char *const IREGS_NAMES[] = {
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"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
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"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
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};
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};
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enum ERegNames {
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enum ERegNames {
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Reg_Zero,
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Reg_Zero,
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Reg_ra,// = 1; // [1] Return address
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Reg_ra, // [1] Return address
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Reg_sp,// = 2; // [2] Stack pointer
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Reg_sp, // [2] Stack pointer
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Reg_gp,// = 3; // [3] Global pointer
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Reg_gp, // [3] Global pointer
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Reg_tp,// = 4; // [4] Thread pointer
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Reg_tp, // [4] Thread pointer
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Reg_t0,// = 5; // [5] Temporaries 0 s3
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Reg_t0, // [5] Temporaries 0 s3
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Reg_t1,// = 6; // [6] Temporaries 1 s4
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Reg_t1, // [6] Temporaries 1 s4
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Reg_t2,// = 7; // [7] Temporaries 2 s5
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Reg_t2, // [7] Temporaries 2 s5
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Reg_s0,// = 8; // [8] s0/fp Saved register/frame pointer
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Reg_s0, // [8] s0/fp Saved register/frame pointer
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Reg_s1,// = 9; // [9] Saved register 1
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Reg_s1, // [9] Saved register 1
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Reg_a0,// = 10; // [10] Function argumentes 0
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Reg_a0, // [10] Function argumentes 0
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Reg_a1,// = 11; // [11] Function argumentes 1
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Reg_a1, // [11] Function argumentes 1
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Reg_a2,// = 12; // [12] Function argumentes 2
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Reg_a2, // [12] Function argumentes 2
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Reg_a3,// = 13; // [13] Function argumentes 3
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Reg_a3, // [13] Function argumentes 3
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Reg_a4,// = 14; // [14] Function argumentes 4
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Reg_a4, // [14] Function argumentes 4
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Reg_a5,// = 15; // [15] Function argumentes 5
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Reg_a5, // [15] Function argumentes 5
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Reg_a6,// = 16; // [16] Function argumentes 6
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Reg_a6, // [16] Function argumentes 6
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Reg_a7,// = 17; // [17] Function argumentes 7
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Reg_a7, // [17] Function argumentes 7
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Reg_s2,// = 18; // [18] Saved register 2
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Reg_s2, // [18] Saved register 2
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Reg_s3,// = 19; // [19] Saved register 3
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Reg_s3, // [19] Saved register 3
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Reg_s4,// = 20; // [20] Saved register 4
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Reg_s4, // [20] Saved register 4
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Reg_s5,// = 21; // [21] Saved register 5
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Reg_s5, // [21] Saved register 5
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Reg_s6,// = 22; // [22] Saved register 6
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Reg_s6, // [22] Saved register 6
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Reg_s7,// = 23; // [23] Saved register 7
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Reg_s7, // [23] Saved register 7
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Reg_s8,// = 24; // [24] Saved register 8
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Reg_s8, // [24] Saved register 8
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Reg_s9,// = 25; // [25] Saved register 9
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Reg_s9, // [25] Saved register 9
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Reg_s10,// = 26; // [26] Saved register 10
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Reg_s10, // [26] Saved register 10
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Reg_s11,// = 27; // [27] Saved register 11
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Reg_s11, // [27] Saved register 11
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Reg_t3,// = 28; // [28]
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Reg_t3, // [28]
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Reg_t4,// = 29; // [29]
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Reg_t4, // [29]
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Reg_t5,// = 30; // [30]
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Reg_t5, // [30]
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Reg_t6,// = 31; // [31]
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Reg_t6, // [31]
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Reg_Total
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Reg_Total
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};
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};
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union csr_mstatus_type {
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union csr_mstatus_type {
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struct bits_type {
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struct bits_type {
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uint64_t UIE : 1; // [0]: User level interrupts ena for current priv. mode
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uint64_t UIE : 1; // [0]: User level interrupts ena for current
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uint64_t SIE : 1; // [1]: Super-User level interrupts ena for current priv. mode
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// priv. mode
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uint64_t HIE : 1; // [2]: Hypervisor level interrupts ena for current priv. mode
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uint64_t SIE : 1; // [1]: Super-User level interrupts ena for
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uint64_t MIE : 1; // [3]: Machine level interrupts ena for current priv. mode
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// current priv. mode
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uint64_t UPIE : 1; // [4]: User level interrupts ena previous value (before interrupt)
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uint64_t HIE : 1; // [2]: Hypervisor level interrupts ena for
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uint64_t SPIE : 1; // [5]: Super-User level interrupts ena previous value (before interrupt)
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// current priv. mode
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uint64_t HPIE : 1; // [6]: Hypervisor level interrupts ena previous value (before interrupt)
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uint64_t MIE : 1; // [3]: Machine level interrupts ena for
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uint64_t MPIE : 1; // [7]: Machine level interrupts ena previous value (before interrupt)
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// current priv. mode
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uint64_t SPP : 1; // [8]: One bit wide. Supper-user previously priviledged level
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uint64_t UPIE : 1; // [4]: User level interrupts ena previous
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uint64_t HPP : 2; // [10:9]: the Hypervisor previous privilege mode
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// value (before interrupt)
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uint64_t MPP : 2; // [12:11]: the Machine previous privilege mode
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uint64_t SPIE : 1; // [5]: Super-User level interrupts ena
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// previous value (before interrupt)
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uint64_t HPIE : 1; // [6]: Hypervisor level interrupts ena
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// previous value (before interrupt)
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uint64_t MPIE : 1; // [7]: Machine level interrupts ena previous
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// value (before interrupt)
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uint64_t SPP : 1; // [8]: One bit wide. Supper-user previously
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// priviledged level
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uint64_t HPP : 2; // [10:9]: the Hypervisor previous priv mode
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uint64_t MPP : 2; // [12:11]: the Machine previous priv mode
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uint64_t FS : 2; // [14:13]: RW: FPU context status
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uint64_t FS : 2; // [14:13]: RW: FPU context status
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uint64_t XS : 2; // [16:15]: RW: extension context status
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uint64_t XS : 2; // [16:15]: RW: extension context status
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uint64_t MPRV : 1; // [17] Memory privilege bit
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uint64_t MPRV : 1; // [17] Memory privilege bit
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uint64_t PUM : 1; // [18]
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uint64_t PUM : 1; // [18]
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uint64_t MXR : 1; // [19]
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uint64_t MXR : 1; // [19]
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uint64_t rsrv1 : 4; // [23:20]
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uint64_t rsrv1 : 4; // [23:20]
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uint64_t VM : 5; // [28:24] Virtualization management field (WARL)
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uint64_t VM : 5; // [28:24] Virtualization management field
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uint64_t rsrv2 : 64-30;// [62:29]
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uint64_t rsv2 : 64-30; // [62:29]
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uint64_t SD : 1; // RO: [63] Bit summarizes FS/XS bits
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uint64_t SD : 1; // RO: [63] Bit summarizes FS/XS bits
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} bits;
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} bits;
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uint64_t value;
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uint64_t value;
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};
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};
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Line 463... |
/** Machine interrupt pending */
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/** Machine interrupt pending */
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static const uint16_t CSR_mip = 0x344;
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static const uint16_t CSR_mip = 0x344;
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/// @}
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/// @}
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/** Exceptions */
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/** Exceptions */
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enum EExeption {
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enum ESignals {
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// Instruction address misaligned
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// Instruction address misaligned
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EXCEPTION_InstrMisalign = 0,
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EXCEPTION_InstrMisalign,
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// Instruction access fault
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// Instruction access fault
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EXCEPTION_InstrFault = 1,
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EXCEPTION_InstrFault,
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// Illegal instruction
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// Illegal instruction
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EXCEPTION_InstrIllegal = 2,
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EXCEPTION_InstrIllegal,
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// Breakpoint
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// Breakpoint
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EXCEPTION_Breakpoint = 3,
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EXCEPTION_Breakpoint,
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// Load address misaligned
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// Load address misaligned
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EXCEPTION_LoadMisalign = 4,
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EXCEPTION_LoadMisalign,
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// Load access fault
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// Load access fault
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EXCEPTION_LoadFault = 5,
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EXCEPTION_LoadFault,
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//Store/AMO address misaligned
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//Store/AMO address misaligned
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EXCEPTION_StoreMisalign = 6,
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EXCEPTION_StoreMisalign,
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// Store/AMO access fault
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// Store/AMO access fault
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EXCEPTION_StoreFault = 7,
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EXCEPTION_StoreFault,
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// Environment call from U-mode
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// Environment call from U-mode
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EXCEPTION_CallFromUmode = 8,
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EXCEPTION_CallFromUmode,
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// Environment call from S-mode
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// Environment call from S-mode
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EXCEPTION_CallFromSmode = 9,
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EXCEPTION_CallFromSmode,
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// Environment call from H-mode
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// Environment call from H-mode
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EXCEPTION_CallFromHmode = 10,
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EXCEPTION_CallFromHmode,
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// Environment call from M-mode
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// Environment call from M-mode
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EXCEPTION_CallFromMmode = 11
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EXCEPTION_CallFromMmode,
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};
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enum EInterrupt {
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// User software interrupt
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// User software interrupt
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INTERRUPT_USoftware = 0,
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INTERRUPT_USoftware,
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// Superuser software interrupt
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// Superuser software interrupt
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INTERRUPT_SSoftware = 1,
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INTERRUPT_SSoftware,
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// Hypervisor software itnerrupt
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// Hypervisor software itnerrupt
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INTERRUPT_HSoftware = 2,
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INTERRUPT_HSoftware,
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// Machine software interrupt
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// Machine software interrupt
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INTERRUPT_MSoftware = 3,
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INTERRUPT_MSoftware,
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// User timer interrupt
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// User timer interrupt
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INTERRUPT_UTimer = 4,
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INTERRUPT_UTimer,
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// Superuser timer interrupt
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// Superuser timer interrupt
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INTERRUPT_STimer = 5,
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INTERRUPT_STimer,
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// Hypervisor timer interrupt
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// Hypervisor timer interrupt
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INTERRUPT_HTimer = 6,
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INTERRUPT_HTimer,
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// Machine timer interrupt
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// Machine timer interrupt
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INTERRUPT_MTimer = 7,
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INTERRUPT_MTimer,
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// User external interrupt
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// User external interrupt
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INTERRUPT_UExternal = 8,
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INTERRUPT_UExternal,
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// Superuser external interrupt
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// Superuser external interrupt
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INTERRUPT_SExternal = 9,
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INTERRUPT_SExternal,
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// Hypervisor external interrupt
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// Hypervisor external interrupt
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INTERRUPT_HExternal = 10,
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INTERRUPT_HExternal,
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// Machine external interrupt (from PLIC)
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// Machine external interrupt (from PLIC)
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INTERRUPT_MExternal = 11,
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INTERRUPT_MExternal,
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SIGNAL_HardReset,
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SIGNAL_Total
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};
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};
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} // namespace debugger
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} // namespace debugger
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#endif // __DEBUGGER_RISCV_ISA_H__
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#endif // __DEBUGGER_RISCV_ISA_H__
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