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* @brief RISC-V extension-F (Floating-point Instructions).
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* @brief RISC-V extension-F (Floating-point Instructions).
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*/
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*/
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#include "api_utils.h"
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#include "api_utils.h"
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#include "riscv-isa.h"
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#include "riscv-isa.h"
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#include "instructions.h"
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#include "cpu_riscv_func.h"
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namespace debugger {
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namespace debugger {
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void addIsaExtensionF(CpuContextType *data, AttributeType *out) {
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void CpuRiver_Functional::addIsaExtensionF() {
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// TODO
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// TODO
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/*
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/*
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addInstr("FADD_S", "0000000??????????????????1010011", NULL, out);
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addInstr("FADD_S", "0000000??????????????????1010011", NULL, out);
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addInstr("FSUB_S", "0000100??????????????????1010011", NULL, out);
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addInstr("FSUB_S", "0000100??????????????????1010011", NULL, out);
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addInstr("FMUL_S", "0001000??????????????????1010011", NULL, out);
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addInstr("FMUL_S", "0001000??????????????????1010011", NULL, out);
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def FSRM = BitPat("b000000000010?????001?????1110011")
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def FSRM = BitPat("b000000000010?????001?????1110011")
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def FSRMI = BitPat("b000000000010?????101?????1110011")
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def FSRMI = BitPat("b000000000010?????101?????1110011")
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def FSCSR = BitPat("b000000000011?????001?????1110011")
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def FSCSR = BitPat("b000000000011?????001?????1110011")
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def FRCSR = BitPat("b00000000001100000010?????1110011")
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def FRCSR = BitPat("b00000000001100000010?????1110011")
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*/
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*/
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data->csr[CSR_misa] |= (1LL << ('F' - 'A'));
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uint64_t isa = portCSR_.read(CSR_misa).val;
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isa |= (1LL << ('F' - 'A'));
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portCSR_.write(CSR_misa, isa);
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}
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}
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} // namespace debugger
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} // namespace debugger
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No newline at end of file
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