URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [cache/] [cache_top.cpp] - Diff between revs 3 and 4

Rev 3	Rev 4
Line 205...	Line 205...

`if (!i_nrst.read()) {`	`if (!i_nrst.read()) {`
`v.state = State_Idle;`	`v.state = State_Idle;`
`}`	`}`

	`w_ctrl_req_ready = 1;`

`o_req_mem_valid = i.req_mem_valid \| d.req_mem_valid;`	`o_req_mem_valid = i.req_mem_valid \| d.req_mem_valid;`
`o_req_mem_write = w_mem_write;`	`o_req_mem_write = w_mem_write;`
`o_req_mem_addr = wb_mem_addr;`	`o_req_mem_addr = wb_mem_addr;`
`o_req_mem_strob = wb_mem_strob;`	`o_req_mem_strob = wb_mem_strob;`
`o_req_mem_data = wb_mem_wdata;`	`o_req_mem_data = wb_mem_wdata;`