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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief Branch Predictor.
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* you may not use this file except in compliance with the License.
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* @details This module gives about 5% of performance improvement (CPI)
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#include "br_predic.h"
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#include "br_predic.h"
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namespace debugger {
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namespace debugger {
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sensitive << i_resp_mem_data;
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sensitive << i_resp_mem_data;
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sensitive << i_f_predic_miss;
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sensitive << i_f_predic_miss;
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sensitive << i_e_npc;
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sensitive << i_e_npc;
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sensitive << i_ra;
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sensitive << i_ra;
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sensitive << r.npc;
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sensitive << r.npc;
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sensitive << r.resp_mem_data;
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sensitive << r.resp_mem_addr;
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SC_METHOD(registers);
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SC_METHOD(registers);
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sensitive << i_clk.pos();
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sensitive << i_clk.pos();
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};
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};
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sc_trace(o_vcd, i_e_npc, "/top/proc0/bp0/i_e_npc");
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sc_trace(o_vcd, i_e_npc, "/top/proc0/bp0/i_e_npc");
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sc_trace(o_vcd, i_ra, "/top/proc0/bp0/i_ra");
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sc_trace(o_vcd, i_ra, "/top/proc0/bp0/i_ra");
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sc_trace(o_vcd, o_npc_predict, "/top/proc0/bp0/o_npc_predict");
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sc_trace(o_vcd, o_npc_predict, "/top/proc0/bp0/o_npc_predict");
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sc_trace(o_vcd, r.npc, "/top/proc0/bp0/r_npc");
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sc_trace(o_vcd, r.npc, "/top/proc0/bp0/r_npc");
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sc_trace(o_vcd, r.resp_mem_data, "/top/proc0/bp0/r_resp_mem_data");
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sc_trace(o_vcd, r.resp_mem_addr, "/top/proc0/bp0/r_resp_mem_addr");
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sc_trace(o_vcd, wb_npc, "/top/proc0/bp0/wb_npc");
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}
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}
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}
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}
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void BranchPredictor::comb() {
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void BranchPredictor::comb() {
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v = r;
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v = r;
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sc_uint<BUS_ADDR_WIDTH> wb_jal_off;
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sc_uint<32> wb_tmp;
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sc_uint<32> wb_tmp;
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sc_uint<BUS_ADDR_WIDTH> wb_npc;
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sc_uint<BUS_ADDR_WIDTH> wb_off;
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wb_tmp = i_resp_mem_data.read();
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if (i_resp_mem_valid.read()) {
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if (i_f_predic_miss.read()) {
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v.resp_mem_addr = i_resp_mem_addr.read();
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wb_npc = i_e_npc.read() + 4;
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v.resp_mem_data = i_resp_mem_data.read();
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} else {
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wb_npc = r.npc.read() + 4;
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}
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}
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wb_tmp = r.resp_mem_data.read();
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wb_npc = r.npc.read();
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if (wb_tmp[31]) {
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if (wb_tmp[31]) {
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wb_off(BUS_ADDR_WIDTH-1, 20) = ~0;
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wb_jal_off(BUS_ADDR_WIDTH-1, 20) = ~0;
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} else {
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} else {
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wb_off(BUS_ADDR_WIDTH-1, 20) = 0;
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wb_jal_off(BUS_ADDR_WIDTH-1, 20) = 0;
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}
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}
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wb_off(19, 12) = wb_tmp(19, 12);
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wb_jal_off(19, 12) = wb_tmp(19, 12);
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wb_off[11] = wb_tmp[20];
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wb_jal_off[11] = wb_tmp[20];
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wb_off(10, 1) = wb_tmp(30, 21);
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wb_jal_off(10, 1) = wb_tmp(30, 21);
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wb_off[0] = 0;
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wb_jal_off[0] = 0;
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if (i_resp_mem_valid.read()) {
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if (i_f_predic_miss.read()) {
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if (wb_tmp == 0x00008067) {
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wb_npc = i_e_npc.read();
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// ret pseudo-instruction: Dhry score 34816 -> 35136
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} else if (wb_tmp == 0x00008067) {
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v.npc = i_ra.read()(BUS_ADDR_WIDTH-1, 0);
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// ret32 pseudo-instruction:
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} else if (wb_tmp(6, 0) == 0x6f) {
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wb_npc = i_ra.read()(BUS_ADDR_WIDTH-1, 0);
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//} else if (wb_tmp(6, 0) == 0x6f) {
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// jal instruction: Dhry score 35136 -> 36992
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// jal instruction: Dhry score 35136 -> 36992
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v.npc = i_resp_mem_addr.read() + wb_off;
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//wb_npc = r.resp_mem_addr.read() + wb_jal_off;
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} else if (i_req_mem_fire.read()) {
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} else {
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v.npc = wb_npc;
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wb_npc = r.npc.read() + 2;
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}
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}
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} else if (i_req_mem_fire.read()) {
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if (i_req_mem_fire.read()) {
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v.npc = wb_npc;
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v.npc = wb_npc;
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}
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}
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if (!i_nrst.read()) {
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if (!i_nrst.read()) {
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v.npc = RESET_VECTOR;
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v.npc = RESET_VECTOR - 2;
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v.resp_mem_addr = RESET_VECTOR;
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v.resp_mem_data = 0;
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}
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}
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o_npc_predict = r.npc;
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o_npc_predict = wb_npc;
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}
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}
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void BranchPredictor::registers() {
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void BranchPredictor::registers() {
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r = v;
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r = v;
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}
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}
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