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/**
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/*
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* @file
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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*
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* Licensed under the Apache License, Version 2.0 (the "License");
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* @brief CPU Instruction Execution stage.
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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*/
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#include "execute.h"
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#include "execute.h"
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#include "riscv-isa.h"
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#include "riscv-isa.h"
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sensitive << i_pipeline_hold;
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sensitive << i_pipeline_hold;
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sensitive << i_d_valid;
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sensitive << i_d_valid;
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sensitive << i_d_pc;
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sensitive << i_d_pc;
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sensitive << i_d_instr;
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sensitive << i_d_instr;
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sensitive << i_wb_done;
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sensitive << i_wb_done;
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sensitive << i_memop_load;
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sensitive << i_memop_store;
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sensitive << i_memop_store;
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sensitive << i_memop_load;
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sensitive << i_memop_sign_ext;
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sensitive << i_memop_sign_ext;
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sensitive << i_memop_size;
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sensitive << i_memop_size;
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sensitive << i_unsigned_op;
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sensitive << i_unsigned_op;
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sensitive << i_rv32;;
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sensitive << i_rv32;
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sensitive << i_compressed;
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sensitive << i_isa_type;
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sensitive << i_isa_type;
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sensitive << i_ivec;
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sensitive << i_ivec;
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sensitive << i_rdata1;
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sensitive << i_rdata2;
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sensitive << i_csr_rdata;
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sensitive << i_ext_irq;
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sensitive << i_ie;
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sensitive << i_ie;
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sensitive << i_mtvec;
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sensitive << i_mtvec;
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sensitive << i_mode;
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sensitive << i_mode;
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sensitive << i_break_mode;
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sensitive << i_break_mode;
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sensitive << i_unsup_exception;
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sensitive << i_unsup_exception;
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sensitive << i_ext_irq;
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sensitive << i_dport_npc_write;
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sensitive << i_dport_npc_write;
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sensitive << i_dport_npc;
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sensitive << i_dport_npc;
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sensitive << i_rdata1;
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sensitive << i_rdata2;
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sensitive << i_csr_rdata;
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sensitive << r.d_valid;
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sensitive << r.d_valid;
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sensitive << r.pc;
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sensitive << r.npc;
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sensitive << r.npc;
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sensitive << r.hazard_depth;
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sensitive << r.instr;
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sensitive << r.hazard_addr0;
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sensitive << r.hazard_addr1;
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sensitive << r.res_val;
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sensitive << r.res_val;
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sensitive << r.memop_load;
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sensitive << r.memop_load;
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sensitive << r.memop_store;
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sensitive << r.memop_store;
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sensitive << w_hazard_detected;
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sensitive << r.memop_addr;
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sensitive << r.multi_res_addr;
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sensitive << r.multi_pc;
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sensitive << r.multi_npc;
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sensitive << r.multi_instr;
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sensitive << r.multi_ena[Multi_MUL];
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sensitive << r.multi_ena[Multi_MUL];
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sensitive << r.multi_ena[Multi_DIV];
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sensitive << r.multi_ena[Multi_DIV];
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sensitive << r.multi_res_addr;
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sensitive << r.multi_rv32;
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sensitive << r.multi_unsigned;
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sensitive << r.multi_residual_high;
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sensitive << r.multiclock_ena;
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sensitive << r.multiclock_ena;
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sensitive << r.multi_a1;
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sensitive << r.multi_a2;
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sensitive << r.hazard_addr0;
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sensitive << r.hazard_addr1;
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sensitive << r.hazard_depth;
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sensitive << r.ext_irq_pulser;
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sensitive << r.trap_ena;
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sensitive << r.trap_ena;
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sensitive << r.breakpoint;
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sensitive << r.breakpoint;
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sensitive << r.trap_code;
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sensitive << r.trap_pc;
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sensitive << r.call;
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sensitive << r.ret;
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sensitive << w_hazard_detected;
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sensitive << wb_arith_res.arr[Multi_MUL];
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sensitive << wb_arith_res.arr[Multi_MUL];
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sensitive << wb_arith_res.arr[Multi_DIV];
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sensitive << wb_arith_res.arr[Multi_DIV];
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sensitive << w_arith_valid[Multi_MUL];
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sensitive << w_arith_valid[Multi_MUL];
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sensitive << w_arith_valid[Multi_DIV];
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sensitive << w_arith_valid[Multi_DIV];
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sensitive << w_arith_busy[Multi_MUL];
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sensitive << w_arith_busy[Multi_DIV];
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sensitive << wb_shifter_a1;
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sensitive << wb_shifter_a2;
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sensitive << wb_sll;
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sensitive << wb_sll;
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sensitive << wb_sllw;
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sensitive << wb_sllw;
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sensitive << wb_srl;
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sensitive << wb_srl;
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sensitive << wb_srlw;
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sensitive << wb_srlw;
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sensitive << wb_sra;
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sensitive << wb_sra;
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bool w_memop_store;
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bool w_memop_store;
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bool w_memop_sign_ext;
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bool w_memop_sign_ext;
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sc_uint<2> wb_memop_size;
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sc_uint<2> wb_memop_size;
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sc_uint<BUS_ADDR_WIDTH> wb_memop_addr;
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sc_uint<BUS_ADDR_WIDTH> wb_memop_addr;
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sc_bv<Instr_Total> wv;
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sc_bv<Instr_Total> wv;
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int opcode_len;
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bool w_pc_valid;
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bool w_pc_valid;
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bool w_d_acceptable;
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bool w_d_acceptable;
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bool w_multi_valid;
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bool w_multi_valid;
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bool w_multi_ena;
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bool w_multi_ena;
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w_gr_equal = 1;
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w_gr_equal = 1;
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}
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}
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// Relative Branch on some condition:
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// Relative Branch on some condition:
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w_pc_branch = 0;
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w_pc_branch = 0;
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if ((wv[Instr_BEQ] & (wb_sub64 == 0))
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if ((wv[Instr_BEQ].to_bool() & (wb_sub64 == 0))
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|| (wv[Instr_BGE] & (wb_sub64[63] == 0))
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|| (wv[Instr_BGE].to_bool() & (wb_sub64[63] == 0))
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|| (wv[Instr_BGEU] & (w_gr_equal))
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|| (wv[Instr_BGEU].to_bool() & (w_gr_equal))
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|| (wv[Instr_BLT] & (wb_sub64[63] == 1))
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|| (wv[Instr_BLT].to_bool() & (wb_sub64[63] == 1))
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|| (wv[Instr_BLTU] & (w_less))
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|| (wv[Instr_BLTU].to_bool() & (w_less))
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|| (wv[Instr_BNE] & (wb_sub64 != 0))) {
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|| (wv[Instr_BNE].to_bool() & (wb_sub64 != 0))) {
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w_pc_branch = 1;
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w_pc_branch = 1;
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}
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}
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opcode_len = 4;
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if (i_compressed.read()) {
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opcode_len = 2;
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}
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if (w_pc_branch) {
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if (w_pc_branch) {
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wb_npc = i_d_pc.read() + wb_off(BUS_ADDR_WIDTH-1, 0);
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wb_npc = i_d_pc.read() + wb_off(BUS_ADDR_WIDTH-1, 0);
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} else if (wv[Instr_JAL].to_bool()) {
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} else if (wv[Instr_JAL].to_bool()) {
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wb_res = i_d_pc.read() + 4;
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wb_res = i_d_pc.read() + opcode_len;
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wb_npc = wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_off(BUS_ADDR_WIDTH-1, 0);
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wb_npc = wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_off(BUS_ADDR_WIDTH-1, 0);
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} else if (wv[Instr_JALR].to_bool()) {
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} else if (wv[Instr_JALR].to_bool()) {
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wb_res = i_d_pc.read() + 4;
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wb_res = i_d_pc.read() + opcode_len;
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wb_npc = wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_rdata2(BUS_ADDR_WIDTH-1, 0);
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wb_npc = wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_rdata2(BUS_ADDR_WIDTH-1, 0);
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wb_npc[0] = 0;
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wb_npc[0] = 0;
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} else if ((wv[Instr_MRET] | wv[Instr_URET]).to_bool()) {
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} else if ((wv[Instr_MRET] | wv[Instr_URET]).to_bool()) {
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wb_res = i_d_pc.read() + 4;
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wb_res = i_d_pc.read() + opcode_len;
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w_xret = i_d_valid;
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w_xret = i_d_valid.read() && w_pc_valid;
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w_csr_wena = 0;
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w_csr_wena = 0;
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if (wv[Instr_URET].to_bool()) {
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if (wv[Instr_URET].to_bool()) {
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wb_csr_addr = CSR_uepc;
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wb_csr_addr = CSR_uepc;
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} else {
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} else {
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wb_csr_addr = CSR_mepc;
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wb_csr_addr = CSR_mepc;
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}
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}
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wb_npc = i_csr_rdata;
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wb_npc = i_csr_rdata;
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} else {
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} else {
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// Instr_HRET, Instr_SRET, Instr_FENCE, Instr_FENCE_I:
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// Instr_HRET, Instr_SRET, Instr_FENCE, Instr_FENCE_I:
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wb_npc = i_d_pc.read() + 4;
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wb_npc = i_d_pc.read() + opcode_len;
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}
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}
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if (i_memop_load) {
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if (i_memop_load) {
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wb_memop_addr =
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wb_memop_addr =
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wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_rdata2(BUS_ADDR_WIDTH-1, 0);
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wb_rdata1(BUS_ADDR_WIDTH-1, 0) + wb_rdata2(BUS_ADDR_WIDTH-1, 0);
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|| (wv[Instr_URET] && i_mode.read() != PRV_U)) {
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|| (wv[Instr_URET] && i_mode.read() != PRV_U)) {
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w_exception_xret = 1;
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w_exception_xret = 1;
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}
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}
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w_exception = w_d_acceptable
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w_exception = w_d_acceptable
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& (i_unsup_exception.read() || w_exception_load || w_exception_store
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& ((i_unsup_exception.read() & w_pc_valid) || w_exception_load
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|| w_exception_xret || wv[Instr_ECALL] || wv[Instr_EBREAK]);
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|| w_exception_store || w_exception_xret
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|| wv[Instr_ECALL] || wv[Instr_EBREAK]);
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/** Default number of cycles per instruction = 0 (1 clock per instr)
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/** Default number of cycles per instruction = 0 (1 clock per instr)
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* If instruction is multicycle then modify this value.
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* If instruction is multicycle then modify this value.
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*/
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*/
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v.multi_ena[Multi_MUL] = 0;
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v.multi_ena[Multi_MUL] = 0;
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Line 556... |
}
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}
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wb_exception_code = 0;
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wb_exception_code = 0;
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if (i_ext_irq & i_ie & !r.ext_irq_pulser) { // Maskable traps (interrupts)
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if (i_ext_irq & i_ie & !r.ext_irq_pulser) { // Maskable traps (interrupts)
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v.trap_code_waiting[4] = 1;
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v.trap_code_waiting[4] = 1;
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v.trap_code_waiting(3, 0) = INTERRUPT_MExternal;
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// INTERRUPT_MExternal - INTERRUPT_USoftware
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v.trap_code_waiting(3, 0) = 11;
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} else if (w_exception) { // Unmaskable traps (exceptions)
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} else if (w_exception) { // Unmaskable traps (exceptions)
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wb_exception_code[4] = 0;
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wb_exception_code[4] = 0;
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if (w_exception_load) {
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if (w_exception_load) {
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wb_exception_code(3, 0) = EXCEPTION_LoadMisalign;
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wb_exception_code(3, 0) = EXCEPTION_LoadMisalign;
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} else if (w_exception_store) {
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} else if (w_exception_store) {
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