URL
https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
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Line 39... |
Line 39... |
brList_ = *resp;
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brList_ = *resp;
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return;
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return;
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}
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}
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uint64_t br_addr = resp->to_uint64();
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uint64_t br_addr = resp->to_uint64();
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uint32_t br_instr = 0;
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uint32_t br_instr = 0;
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bool br_hw;
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uint64_t br_flags;
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for (unsigned i = 0; i < brList_.size(); i++) {
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for (unsigned i = 0; i < brList_.size(); i++) {
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const AttributeType &br = brList_[i];
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const AttributeType &br = brList_[i];
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if (br_addr == br[BrkList_address].to_uint64()) {
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if (br_addr == br[BrkList_address].to_uint64()) {
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br_instr = br[BrkList_instr].to_int();
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br_instr = br[BrkList_instr].to_int();
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br_hw = br[BrkList_hwflag].to_bool();
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br_flags = br[BrkList_flags].to_uint64();
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break;
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break;
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}
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}
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}
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}
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if (br_instr == 0) {
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if (br_instr == 0) {
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return;
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return;
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}
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}
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if (br_hw) {
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if (br_flags & BreakFlag_HW) {
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RISCV_sprintf(tstr, sizeof(tstr),
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RISCV_sprintf(tstr, sizeof(tstr),
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"write 0x%08" RV_PRI64 "x 8 0x%" RV_PRI64 "x",
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"write 0x%08" RV_PRI64 "x 8 0x%" RV_PRI64 "x",
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dsu_hw_br_, br_addr);
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dsu_hw_br_, br_addr);
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} else {
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} else {
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RISCV_sprintf(tstr, sizeof(tstr),
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RISCV_sprintf(tstr, sizeof(tstr),
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