URL
https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
Show entire file |
Details |
Blame |
View Log
Rev 3 |
Rev 4 |
Line 33... |
Line 33... |
generateError(res, "Wrong argument list");
|
generateError(res, "Wrong argument list");
|
return;
|
return;
|
}
|
}
|
|
|
Reg64Type t1;
|
Reg64Type t1;
|
DsuMapType::udbg_type::debug_region_type::control_reg ctrl;
|
GenericCpuControlType ctrl;
|
DsuMapType *pdsu = info_->getpDsu();
|
DsuMapType *pdsu = info_->getpDsu();
|
uint64_t addr = reinterpret_cast<uint64_t>(&pdsu->udbg.v.control);
|
uint64_t addr = reinterpret_cast<uint64_t>(&pdsu->udbg.v.control);
|
tap_->read(addr, 8, t1.buf);
|
tap_->read(addr, 8, t1.buf);
|
ctrl.val = t1.val;
|
ctrl.val = t1.val;
|
if (ctrl.bits.halt) {
|
if (ctrl.bits.halt) {
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.