URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [libdbg64g/] [services/] [mem/] [memsim.h] - Diff between revs 2 and 4

Rev 2	Rev 4
Line 22...	Line 22...

`/** IService interface */`	`/** IService interface */`
`virtual void postinitService();`	`virtual void postinitService();`

`/** IMemoryOperation */`	`/** IMemoryOperation */`
`virtual void b_transport(Axi4TransactionType *trans);`	`virtual ETransStatus b_transport(Axi4TransactionType *trans);`

`virtual uint64_t getBaseAddress() {`
`return baseAddress_.to_uint64();`
`}`
`virtual uint64_t getLength() {`
`return length_.to_uint64();`
`}`

`private:`	`private:`
`static const int SYMB_IN_LINE = 16/2;`	`static const int SYMB_IN_LINE = 16/2;`
`bool chishex(int s);`	`bool chishex(int s);`
`uint8_t chtohex(int s);`	`uint8_t chtohex(int s);`

`private:`	`private:`
`AttributeType initFile_;`	`AttributeType initFile_;`
`AttributeType readOnly_;`	`AttributeType readOnly_;`
`AttributeType baseAddress_;`	`AttributeType binaryFile_;`
`AttributeType length_;`
`uint8_t *mem_;`	`uint8_t *mem_;`
`};`	`};`

`DECLARE_CLASS(MemorySim)`	`DECLARE_CLASS(MemorySim)`