URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [fsev2.h] - Diff between revs 2 and 4

Rev 2	Rev 4
Line 18...	Line 18...
`public IMemoryOperation {`	`public IMemoryOperation {`
`public:`	`public:`
`FseV2(const char *name);`	`FseV2(const char *name);`

`/** IMemoryOperation */`	`/** IMemoryOperation */`
`virtual void b_transport(Axi4TransactionType *trans);`	`virtual ETransStatus b_transport(Axi4TransactionType *trans);`

`virtual uint64_t getBaseAddress() {`
`return baseAddress_.to_uint64();`
`}`
`virtual uint64_t getLength() {`
`return length_.to_uint64();`
`}`

`private:`	`private:`
`AttributeType baseAddress_;`
`AttributeType length_;`

`static const int FSE2_CHAN_MAX = 32;`	`static const int FSE2_CHAN_MAX = 32;`

`struct fsev2_chan_fields {`	`struct fsev2_chan_fields {`
`volatile uint32_t common;//prn, acc_ms, carr_steps, coh_ena`	`volatile uint32_t common;//prn, acc_ms, carr_steps, coh_ena`
`volatile int32_t carr_nco_f0;`	`volatile int32_t carr_nco_f0;`