URL https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk

Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [socsim_plugin/] [gnss_stub.h] - Diff between revs 2 and 4

Rev 2	Rev 4
Line 26...	Line 26...

`/** IService interface */`	`/** IService interface */`
`virtual void postinitService();`	`virtual void postinitService();`

`/** IMemoryOperation */`	`/** IMemoryOperation */`
`virtual void b_transport(Axi4TransactionType *trans);`	`virtual ETransStatus b_transport(Axi4TransactionType *trans);`

`virtual uint64_t getBaseAddress() {`
`return baseAddress_.to_uint64();`
`}`
`virtual uint64_t getLength() {`
`return length_.to_uint64();`
`}`

`/** IClockListener */`	`/** IClockListener */`
`virtual void stepCallback(uint64_t t);`	`virtual void stepCallback(uint64_t t);`

`private:`	`private:`
Line 45...	Line 38...
`return reinterpret_cast<uint64_t>(addr)`	`return reinterpret_cast<uint64_t>(addr)`
`- reinterpret_cast<uint64_t>(&regs_);`	`- reinterpret_cast<uint64_t>(&regs_);`
`}`	`}`

`private:`	`private:`
`AttributeType baseAddress_;`
`AttributeType length_;`
`AttributeType irqLine_;`
`AttributeType irqctrl_;`	`AttributeType irqctrl_;`
`AttributeType clksrc_;`	`AttributeType clksrc_;`
`IWire *iwire_;`	`IWire *iwire_;`
`IClock *iclk_;`	`IClock *iclk_;`