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*/
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*/
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#ifndef __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
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#ifndef __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
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#define __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
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#define __DEBUGGER_SOCSIM_PLUGIN_IRQCTRL_H__
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#include "iclass.h"
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#include <iclass.h>
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#include "iservice.h"
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#include <iservice.h>
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#include "coreservices/iclock.h"
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#include "coreservices/imemop.h"
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#include "coreservices/imemop.h"
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#include "coreservices/iwire.h"
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#include "coreservices/iwire.h"
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#include "coreservices/icpuriscv.h"
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#include "coreservices/icpugen.h"
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namespace debugger {
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namespace debugger {
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class IrqPort : public IWire {
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public:
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IrqPort(IService *parent, const char *portname, int idx);
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/** IWire interface */
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virtual void raiseLine();
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virtual void lowerLine() { level_ = false; }
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virtual void setLevel(bool level);
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virtual bool getLevel() { return level_; }
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protected:
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IService *parent_;
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int idx_;
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bool level_;
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};
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class IrqController : public IService,
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class IrqController : public IService,
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public IMemoryOperation,
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public IMemoryOperation,
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public IWire {
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public IClockListener {
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public:
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public:
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IrqController(const char *name);
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IrqController(const char *name);
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~IrqController();
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~IrqController();
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/** IService interface */
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/** IService interface */
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virtual void postinitService();
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virtual void postinitService();
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/** IMemoryOperation */
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/** IMemoryOperation */
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virtual void b_transport(Axi4TransactionType *payload);
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virtual ETransStatus b_transport(Axi4TransactionType *payload);
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/** IClockListener interface */
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virtual void stepCallback(uint64_t t);
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virtual uint64_t getBaseAddress() {
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/** Controller specific methods visible for ports */
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return baseAddress_.to_uint64();
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void requestInterrupt(int idx);
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}
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virtual uint64_t getLength() {
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return length_.to_uint64();
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}
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/** IWire */
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virtual void raiseLine(int idx);
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virtual void lowerLine() {}
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virtual void setLevel(bool level) {}
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private:
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private:
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AttributeType baseAddress_;
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AttributeType length_;
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AttributeType mipi_;
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AttributeType mipi_;
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AttributeType irqTotal_;
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AttributeType irqTotal_;
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AttributeType cpu_;
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AttributeType cpu_;
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ICpuRiscV *icpu_;
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ICpuGeneric *icpu_;
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IClock *iclk_;
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static const int IRQ_MAX = 32;
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IrqPort *irqlines_[IRQ_MAX];
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struct irqctrl_map {
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struct irqctrl_map {
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uint32_t irq_mask; // 0x00: [RW] 1=disable; 0=enable
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uint32_t irq_mask; // 0x00: [RW] 1=disable; 0=enable
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uint32_t irq_pending; // 0x04: [RW]
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uint32_t irq_pending; // 0x04: [RW]
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uint32_t irq_clear; // 0x08: [WO]
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uint32_t irq_clear; // 0x08: [WO]
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uint64_t dbg_cause; // 0x18: [RW]
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uint64_t dbg_cause; // 0x18: [RW]
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uint64_t dbg_epc; // 0x20: [RW]
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uint64_t dbg_epc; // 0x20: [RW]
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uint32_t irq_lock; // 0x28: [RW]
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uint32_t irq_lock; // 0x28: [RW]
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uint32_t irq_cause_idx; // 0x2c: [RW]
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uint32_t irq_cause_idx; // 0x2c: [RW]
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} regs_;
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} regs_;
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uint32_t irq_wait_unlock;
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};
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};
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DECLARE_CLASS(IrqController)
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DECLARE_CLASS(IrqController)
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} // namespace debugger
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} // namespace debugger
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