URL https://opencores.org/ocsvn/robust_axi2apb/robust_axi2apb/trunk

Subversion Repositories robust_axi2apb

[/] [robust_axi2apb/] [trunk/] [src/] [base/] [axi2apb_mux.v] - Diff between revs 4 and 8

Rev 4	Rev 8
Line 26...	Line 26...
`//// details. http://www.gnu.org/licenses/lgpl.html ////`	`//// details. http://www.gnu.org/licenses/lgpl.html ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////##>`	`//////////////////////////////////////////////////////////////////##>`

`INCLUDE def_axi2apb.txt`	`INCLUDE def_axi2apb.txt`
`OUTFILE PREFIX_axi2apb_mux.v`	`OUTFILE PREFIX_mux.v`

`ITER SX`	`ITER SX`
`module PREFIX_axi2apb_mux (PORTS);`	`module PREFIX_mux (PORTS);`


`input clk;`	`input clk;`
`input reset;`	`input reset;`

Line 66...	Line 66...
`reg [SLV_BITS-1:0] slave_num;`	`reg [SLV_BITS-1:0] slave_num;`

`always @(*)`	`always @(*)`
`begin`	`begin`
`casex (cmd_addr[ADDR_MSB:ADDR_LSB])`	`casex (cmd_addr[ADDR_MSB:ADDR_LSB])`
`DEC_ADDRSX : slave_num = SLV_BITS'dSX;`	`DEC_BITSDEC_ADDRSX : slave_num = SLV_BITS'dSX;`

`default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error`	`default : slave_num = SLV_BITS'dSLAVE_NUM; //decode error`
`endcase`	`endcase`
`end`	`end`