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Subversion Repositories rs232_with_buffer_and_wb

[/] [rs232_with_buffer_and_wb/] [trunk/] [doc/] [RS232_text.txt] - Diff between revs 35 and 40

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Rev 35 Rev 40
?rev1line?
?rev2line?
 
                                                        |                        Period Count                   |
 
                                                        -------------------------------------
 
Baud rate       |       bit period      |       50Mhz   |       100Mhz  |       200Mhz  |
 
-----------------------------------------------------------------
 
2400            |       416.66 mSec     |       20833   |       41667   |         X             |
 
4800            |       208.33 mSec     |       10417   |       20833   |       41667   |
 
9600            |       104.16 mSec     |       5208    |       10417   |       20833   |
 
14400           |
 
19200           |
 
28800           |
 
38400           |
 
57600           |
 
76800           |
 
115200          |       8.68 mSec       |       434             |       868             |       1736    |
 
230400          |       4.34 mSec       |       217             |       434             |       868             |
 
 
 
 
 
 
 
 
 
Signal          | bit
 
------------|----------
 
start           | 1
 
data            | 5,6,7,8
 
Partition       | 1
 
stop            | 1, 1.5, 2
 
 
 
 
 
Signals/Interrupts
 
        RX Buffer empty
 
        RX Buffer full
 
        TX Buffer empty
 
        TX Buffer full
 
        TX Sending
 
 
 
Buffers
 
        RX FIFO Buffer 0-64 Word buffer
 
        TX FIFO Buffer 0-64 Word buffer
 
 
 
After Reset
 
        50MHz 2400bps, 100MHz 4800bps
 
        1 start bit, 8 data bit, 1 stop bit
 
 
 
Componenter
 
        Main()
 
                RS232
 
                        uart_rx
 
                        uart_tx
 
                BUFFER
 
                        rx_fifo
 
                        tx_fifo
 
                WishBone
 
                        uart_setup
 
                        wb_interface
 
 
 
Addresses
 
        00000000 = rx_fifo(r)(rx_fifo_rst.u) / write tx_fifo(w)(tx_fifo_rst.u)
 
        00000001 = |xxxxxxx|rx enable(r/w)(setup_rst.0)|
 
 
 
        00000010 = rx_fifo_entries_back(r)(fifo_rst.fifo_size)
 
        00000011 = tx_fifo_entries_back(r)(fifo_rst.fifo_size)
 
 
 
        00000100 = |rx_idle_line_lvl(r/w)(setup_rst.1)|use_parity_bit(r/w)(setup_rst.0)|parity_type(r/w)(setup_rst.0)|rx_stop_bits(r/w)(setup_rst.01)|word_width(r/w)(setup_rst.000)|
 
 
 
        00000101 = |start_sample(r/w)(setup_rst.0110)|sample_line(r/w)(setup_rst.0100)|
 
 
 
        00000110 = period low  LSB ( 7 downto 0)  (Baud / Frequenzy, min 32, max 655??)
 
 
 
        00000111 = period high MSB (15 downto 8)
 
 
 
        00001000 = |uuu|rst_rx(r/w)(setup_rst.0)|rst_rx_fifo(r/w)(setup_rst.0)|rst_tx(r/w)(setup_rst.0)|rst_fifo_tx(r/w)(setup_rst.0)|rst_setup(r/w)(setup_rst.0)|
 
 
 
        00001001 = |uuu|rst_rx_if_rst_wb(r/w)(setup_rst.0)|rst_rx_fifo_if_rst_wb(r/w)(setup_rst.0)|rst_tx_if_rst_wb(r/w)(setup_rst.0)|rst_fifo_tx_if_rst_wb(r/w)(setup_rst.0)|rst_setup_if_rst_wb(r/w)(setup_rst.0)|
 
 
 
rst_wb.x, Reset of WishBone interface with the following value
 
rst_rx_fifo.x, ReSeT of RX_FIFO with the following value
 
rst_tx_fifo.x, ReSeT of TX_FIFO with the following value
 
u is unknown
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