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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uart_top is
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generic(address_width : integer := 3);
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port( clk, master_rst : in std_logic;
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RST_I : in std_logic;
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ADR_I : in std_logic_vector(7 downto 0);
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DAT_I : in std_logic_vector(7 downto 0);
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WE_I : in std_logic;
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STB_I : in std_logic;
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CYC_I : in std_logic;
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DAT_O : out std_logic_vector(7 downto 0);
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ACK_O : out std_logic;
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rx : in std_logic;
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tx : out std_logic;
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rx_fifo_empty : out std_logic;
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rx_fifo_full : out std_logic;
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tx_fifo_empty : out std_logic;
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tx_fifo_full : out std_logic;
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parity_error : out std_logic;
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stop_bit_error : out std_logic;
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transmitting : out std_logic);
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end entity uart_top;
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architecture behaviour of uart_top is
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component uart_wb is
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port( --WB interface
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CLK_I : in std_logic;
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master_rst : in std_logic;
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RST_I : in std_logic;
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ADR_I : in std_logic_vector(7 downto 0);
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DAT_I : in std_logic_vector(7 downto 0);
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WE_I : in std_logic;
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STB_I : in std_logic;
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CYC_I : in std_logic;
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DAT_O : out std_logic_vector(7 downto 0);
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ACK_O : out std_logic;
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--uart controll
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word_width : out std_logic_vector(3 downto 0);
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baud_period : out std_logic_vector(15 downto 0);
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use_parity_bit : out std_logic;
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parity_type : out std_logic;
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stop_bits : out std_logic_vector(1 downto 0);
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idle_line_lvl : out std_logic;
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rx_enable : out std_logic; --rx specific
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start_samples : out std_logic_vector(3 downto 0); --rx specific
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line_samples : out std_logic_vector(3 downto 0); --rx specific
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uart_rx_rst : out std_logic;
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uart_rx_fifo_rst : out std_logic;
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uart_tx_rst : out std_logic;
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uart_tx_fifo_rst : out std_logic;
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--FIFO control/data
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tx_fifo_entries_free : in std_logic_vector (7 downto 0);
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write_tx_data : out std_logic;
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tx_data : out std_logic_vector(7 downto 0);
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read_rx_data : out std_logic;
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rx_data : in std_logic_vector(7 downto 0);
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rx_fifo_entries_free : in std_logic_vector (7 downto 0));
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end component;
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component tx_func is
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port( clk, reset : in std_logic;
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data : in std_logic_vector(7 downto 0);
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transmit_data : in std_logic;
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word_width : in std_logic_vector(3 downto 0);
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baud_period : in std_logic_vector(15 downto 0);
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use_parity_bit, parity_type : in std_logic;
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stop_bits : in std_logic_vector(1 downto 0);
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idle_line_lvl : in std_logic;
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tx : out std_logic;
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sending : out std_logic);
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end component;
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component rx_func is
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port( clk, reset, rx_enable : in std_logic;
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rx : in std_logic;
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word_width : in std_logic_vector(3 downto 0);
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baud_period : in std_logic_vector(15 downto 0);
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use_parity_bit, parity_type : in std_logic;
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stop_bits : in std_logic_vector(1 downto 0);
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idle_line_lvl : in std_logic;
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start_samples : in std_logic_vector(3 downto 0); --How many correct samples should give a start bit
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line_samples : in std_logic_vector(3 downto 0); --How many samples should tip the internal rx value
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data : out std_logic_vector(7 downto 0);
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data_ready : out std_logic;
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parity_error : out std_logic;
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stop_bit_error : out std_logic);
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end component;
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component rx_fifo is
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generic(address_width : integer := 3);
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port( clk, reset : in std_logic;
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read_rx_data : in std_logic;
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rx_data : out std_logic_vector(7 downto 0);
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rx_fifo_full : out std_logic;
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rx_fifo_empty : out std_logic;
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rx_fifo_entries_free : out std_logic_vector(7 downto 0);
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rx_func_data : in std_logic_vector(7 downto 0);
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rx_func_data_ready : in std_logic);
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end component;
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component tx_fifo is
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generic(address_width : integer := 3);
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port( clk, reset : in std_logic;
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write_tx_data : in std_logic;
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tx_data : in std_logic_vector(7 downto 0);
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tx_fifo_full : out std_logic;
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tx_fifo_empty : out std_logic;
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tx_fifo_entries_free : out std_logic_vector(7 downto 0);
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tx_func_data : out std_logic_vector(7 downto 0);
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tx_func_apply_data : out std_logic;
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tx_func_sending : in std_logic);
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end component;
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signal word_width : std_logic_vector(3 downto 0);
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signal baud_period : std_logic_vector(15 downto 0);
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signal start_samples, line_samples : std_logic_vector(3 downto 0);
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signal use_parity_bit, parity_type, idle_line_lvl : std_logic;
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signal uart_rx_rst, uart_tx_rst, uart_rx_fifo_rst, uart_tx_fifo_rst : std_logic;
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signal rx_fifo_entries_free, tx_fifo_entries_free : std_logic_vector(7 downto 0);
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signal read_rx_data, write_tx_data : std_logic;
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signal tx_data, rx_data : std_logic_vector(7 downto 0);
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signal sending : std_logic;
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signal stop_bits : std_logic_vector(1 downto 0);
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signal rx_func_data, tx_func_data : std_logic_vector(7 downto 0);
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signal rx_func_data_ready, tx_func_apply_data : std_logic;
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signal rx_enable: std_logic;
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begin
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transmitting <= sending;
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wishBoneInterFace : uart_wb port map (clk, master_rst, RST_I,ADR_I,DAT_I,WE_I,STB_I,CYC_I,DAT_O,ACK_O,word_width,baud_period,use_parity_bit,parity_type,stop_bits,idle_line_lvl,rx_enable,start_samples,line_samples,uart_rx_rst,uart_rx_fifo_rst,uart_tx_rst,uart_tx_fifo_rst,tx_fifo_entries_free,write_tx_data,tx_data,read_rx_data,rx_data,rx_fifo_entries_free);
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UartRx : rx_func port map (clk, uart_rx_rst, rx_enable, rx, word_width, baud_period, use_parity_bit, parity_type, stop_bits, idle_line_lvl, start_samples, line_samples, rx_func_data, rx_func_data_ready,parity_error,stop_bit_error);
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UartTx : tx_func port map(clk, uart_tx_rst, tx_func_data, tx_func_apply_data,word_width,baud_period,use_parity_bit, parity_type,stop_bits,idle_line_lvl,tx,sending);
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RxFifo : rx_fifo generic map(address_width) port map(clk, uart_rx_fifo_rst, read_rx_data, rx_data, rx_fifo_full, rx_fifo_empty, rx_fifo_entries_free, rx_func_data, rx_func_data_ready);
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TxFifo : tx_fifo generic map(address_width) port map(clk, uart_tx_fifo_rst, write_tx_data,tx_data,tx_fifo_full,tx_fifo_empty,tx_fifo_entries_free,tx_func_data,tx_func_apply_data,sending);
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end architecture behaviour;
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