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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity tx_fifo is
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generic(address_width : integer := 3);
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port( clk, reset : in std_logic;
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write_tx_data : in std_logic;
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tx_data : in std_logic_vector(7 downto 0);
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tx_fifo_full : out std_logic;
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tx_fifo_empty : out std_logic;
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tx_fifo_entries_free : out std_logic_vector(7 downto 0);
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tx_func_data : out std_logic_vector(7 downto 0);
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tx_func_apply_data : out std_logic;
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tx_func_sending : in std_logic);
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end entity tx_fifo;
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architecture behaviour of tx_fifo is
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type ram_type is array (0 to 2**address_width-1) of std_logic_vector(7 downto 0);
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signal ram : ram_type;
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constant max_fifo_entries : std_logic_vector(address_width downto 0) := conv_std_logic_vector(2**address_width, address_width+1);
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signal tx_entries_back_d : std_logic_vector(address_width downto 0);
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signal tx_entries_back_q : std_logic_vector(address_width downto 0) := max_fifo_entries ;
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signal tx_in_addr_d, tx_out_addr_d : std_logic_vector(address_width-1 downto 0);
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signal tx_in_addr_q, tx_out_addr_q : std_logic_vector(address_width-1 downto 0) := (others => '0');
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signal ram_we : std_logic;
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signal ram_address : std_logic_vector(address_width-1 downto 0) := (others => '0');
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signal tx_fifo_empty_i : std_logic := '1';
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signal tx_fifo_full_i : std_logic := '0';
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signal tx_func_apply_data_i : std_logic;
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begin
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--------------------
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-- Component used --
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--------------------
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-------------------------
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-- Combinational Logic --
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-------------------------
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ram_we <= write_tx_data and not tx_fifo_full_i;
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-- ram_we <= '1' when write_tx_data = '1' and tx_fifo_full_i = '0' else
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-- '0';
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with ram_we select
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ram_address <= tx_in_addr_q when '1',
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tx_out_addr_q when '0',
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tx_out_addr_q when others;
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tx_in_addr_d <= (others => '0') when reset = '1' else
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tx_in_addr_q + 1;-- when ram_we = '1' else --taken care of by the register enable
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--tx_in_addr_q;
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tx_out_addr_d <= (others => '0') when reset = '1' else
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tx_out_addr_q + 1;-- when tx_func_apply_data_i = '1' else
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--tx_out_addr_q;
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tx_func_apply_data <= tx_func_apply_data_i;
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tx_func_apply_data_i <= not(ram_we or tx_func_sending or tx_fifo_empty_i);
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-- tx_func_apply_data_i <= '1' when ram_we = '0' and tx_func_sending = '0' and tx_fifo_empty_i = '0' else
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-- '0';
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tx_fifo_empty <= tx_fifo_empty_i;
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tx_fifo_empty_i <= '0' when tx_entries_back_q /= max_fifo_entries else
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'1';
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tx_fifo_full <= tx_fifo_full_i;
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tx_fifo_full_i <= '0' when tx_entries_back_q /= conv_std_logic_vector(0, address_width+1) else
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'1';
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tx_fifo_entries_free <= conv_std_logic_vector(0,7-address_width) & tx_entries_back_q;
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tx_entries_back_d <= max_fifo_entries when reset = '1' else
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tx_entries_back_q - 1 when ram_we = '1' else
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tx_entries_back_q + 1;-- when tx_func_apply_data_i = '1' else
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--tx_entries_back_q;
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--------------------
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-- Register Logic --
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--------------------
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reg_control : process(clk, reset, ram_we, tx_func_apply_data_i, tx_data)
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begin
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if rising_edge(clk) then
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if reset = '1' or ram_we = '1' or tx_func_apply_data_i = '1' then
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tx_entries_back_q <= tx_entries_back_d;
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end if;
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if reset = '1' or tx_func_apply_data_i = '1' then
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tx_out_addr_q <= tx_out_addr_d;
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end if;
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if reset = '1' or ram_we = '1' then
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tx_in_addr_q <= tx_in_addr_d;
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end if;
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end if;
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end process reg_control;
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-----------------------------------
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-- RAM synchronous - single port --
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-----------------------------------
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ram_control : process(clk, ram_we, ram_address, tx_data)
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begin
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if rising_edge(clk) then
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if ram_we = '1' then
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ram(conv_integer(ram_address)) <= tx_data;
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end if;
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end if;
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end process ram_control;
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tx_func_data <= ram(conv_integer(ram_address));
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end architecture behaviour;
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