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------------------------------------------------------------------------
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-- File infomation
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------------------------------------------------------------------------
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-- Tobias N. Jeppe - 22-01-2013
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-- Wish Bone interface
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-- Implemented with standard single write cycle and single read cycle
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-- 8 bit address, 8 bit in and out put data
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--
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------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uart_wb is
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port( --WB interface
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CLK_I : in std_logic;
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master_rst : in std_logic;
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RST_I : in std_logic;
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ADR_I : in std_logic_vector(7 downto 0);
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DAT_I : in std_logic_vector(7 downto 0);
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WE_I : in std_logic;
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STB_I : in std_logic;
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CYC_I : in std_logic;
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DAT_O : out std_logic_vector(7 downto 0);
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ACK_O : out std_logic;
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--uart controll
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word_width : out std_logic_vector(3 downto 0);
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baud_period : out std_logic_vector(15 downto 0);
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use_parity_bit : out std_logic;
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parity_type : out std_logic;
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stop_bits : out std_logic_vector(1 downto 0);
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idle_line_lvl : out std_logic;
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rx_enable : out std_logic; --rx specific
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start_samples : out std_logic_vector(3 downto 0); --rx specific
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line_samples : out std_logic_vector(3 downto 0); --rx specific
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uart_rx_rst : out std_logic;
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uart_rx_fifo_rst : out std_logic;
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uart_tx_rst : out std_logic;
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uart_tx_fifo_rst : out std_logic;
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--FIFO control/data
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tx_fifo_entries_free : in std_logic_vector (7 downto 0);
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write_tx_data : out std_logic;
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tx_data : out std_logic_vector(7 downto 0);
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read_rx_data : out std_logic;
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rx_data : in std_logic_vector(7 downto 0);
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rx_fifo_entries_free : in std_logic_vector (7 downto 0));
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end entity uart_wb;
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architecture behaviour of uart_wb is
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-- Components
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-- Signals
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signal we_ok : std_logic;
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signal uart_setup_rst : std_logic;
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signal write_reg_addr_1 : std_logic;
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signal reg_addr_1_q, reg_addr_1_d : std_logic;
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signal write_reg_addr_100 : std_logic;
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signal reg_addr_100_q, reg_addr_100_d : std_logic_vector(7 downto 0); --00000100 = rx_idle_line_lvl(r/w)(rst.1)|x|rx_use_parity(r/w)(rst.0)|rx_parity_type|rx_stop_bits(rw)(rst.01)|word_width
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signal write_reg_addr_101 : std_logic;
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signal reg_addr_101_q, reg_addr_101_d : std_logic_vector(7 downto 0); --00000101 = start_samples(4) | reg_samples(4)
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signal write_reg_addr_110 : std_logic;
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signal reg_addr_110_q, reg_addr_110_d : std_logic_vector(7 downto 0); --00000110 = period low LSB ( 7 downto 0) (Baud / Frequenzy, min 32, max 655??)
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signal write_reg_addr_111 : std_logic;
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signal reg_addr_111_q, reg_addr_111_d : std_logic_vector(7 downto 0); --00000111 = period high MSB (15 downto 8)
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signal write_reg_addr_1000 : std_logic;
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signal reg_addr_1000_q, reg_addr_1000_d : std_logic_vector(4 downto 0); --00001000 = xxx | rst_uart_rx | rst_uart_rx_fifo | rst_uart_tx | rst_uart_tx_fifo | rst_uart_setup
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signal write_reg_addr_1001 : std_logic;
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signal reg_addr_1001_q : std_logic_vector(4 downto 0);-- := "11111"; --00001001 = xxx | rst_uart_rx_if_rst_wb | rst_uart_rx_fifo_if_rst_wb | rst_uart_tx_if_rst_wb | rst_uart_tx_fifo_if_rst_wb | rst_uart_setup_if_rst_wb |
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signal reg_addr_1001_d : std_logic_vector(4 downto 0);
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Begin
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-------------------------
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-- Combinational Logic --
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-------------------------
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we_ok <= WE_I and CYC_I;
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ACK_O <= STB_I;
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--DAT_O asynchronous
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with ADR_I select
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DAT_O <= "0000000" & reg_addr_1_q when "00000001",
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rx_fifo_entries_free when "00000010",
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tx_fifo_entries_free when "00000011",
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reg_addr_100_q when "00000100",
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reg_addr_101_q when "00000101",
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reg_addr_110_q when "00000110",
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reg_addr_111_q when "00000111",
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"000" & reg_addr_1000_q when "00001000",
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"000" & reg_addr_1001_q when "00001001",
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rx_data when others;
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rx_enable <= reg_addr_1_q;
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write_reg_addr_1 <= '1' when (ADR_I = "00000001" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_1_d <= '0' when uart_setup_rst = '1' else
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DAT_I(0);
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idle_line_lvl <= reg_addr_100_q(7);
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use_parity_bit <= reg_addr_100_q(6);
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parity_type <= reg_addr_100_q(5);
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stop_bits <= reg_addr_100_q(4 downto 3);
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word_width <= '0' & reg_addr_100_q(2 downto 0); --the msb is missing
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write_reg_addr_100 <= '1' when (ADR_I = "00000100" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_100_d <= "10001000" when uart_setup_rst = '1' else
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DAT_I;
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start_samples <= reg_addr_101_q(7 downto 4);
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line_samples <= reg_addr_101_q(3 downto 0);
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write_reg_addr_101 <= '1' when (ADR_I = "00000101" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_101_d <= "0110" & "0100" when uart_setup_rst = '1' else
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DAT_I;
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baud_period <= reg_addr_111_q & reg_addr_110_q;
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write_reg_addr_110 <= '1' when (ADR_I = "00000110" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_110_d <= "00010000" when uart_setup_rst = '1' else
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DAT_I;
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write_reg_addr_111 <= '1' when (ADR_I = "00000111" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_111_d <= "00000000" when uart_setup_rst = '1' else
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DAT_I;
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uart_rx_rst <= (RST_I and reg_addr_1001_q(4)) or reg_addr_1000_q(4) or master_rst;
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uart_rx_fifo_rst <= (RST_I and reg_addr_1001_q(3)) or reg_addr_1000_q(3) or master_rst;
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uart_tx_rst <= (RST_I and reg_addr_1001_q(2)) or reg_addr_1000_q(2) or master_rst;
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uart_tx_fifo_rst <= (RST_I and reg_addr_1001_q(1)) or reg_addr_1000_q(1) or master_rst;
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uart_setup_rst <= (RST_I and reg_addr_1001_q(0)) or reg_addr_1000_q(0) or master_rst;
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write_reg_addr_1000 <= '1' when (ADR_I = "00001000" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_1000_d <= "00000" when uart_setup_rst = '1' else
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DAT_I(4 downto 0);
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write_reg_addr_1001 <= '1' when (ADR_I = "00001001" and we_ok = '1') or uart_setup_rst = '1' else
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'0';
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reg_addr_1001_d <= "11111" when uart_setup_rst = '1' else
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DAT_I(4 downto 0);
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--Write to tx_fifo
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write_tx_data <= '1' when ADR_I = "00000000" and we_ok = '1' else '0';
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tx_data <= DAT_I;
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--Read from rx_fifo
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read_rx_data <= '1' when ADR_I = "00000000" and (WE_I='0' and CYC_I = '1') else '0';
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--------------------
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-- Register Logic --
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--------------------
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register_logic : process(CLK_I, write_reg_addr_100, write_reg_addr_101, write_reg_addr_110,write_reg_addr_111,write_reg_addr_1000,write_reg_addr_1001)
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begin
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if rising_edge(CLK_I) then
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if write_reg_addr_1 = '1' then
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reg_addr_1_q <= reg_addr_1_d;
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end if;
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if write_reg_addr_100 = '1' then
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reg_addr_100_q <= reg_addr_100_d;
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end if;
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if write_reg_addr_101 = '1' then
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reg_addr_101_q <= reg_addr_101_d;
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end if;
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if write_reg_addr_110 = '1' then
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reg_addr_110_q <= reg_addr_110_d;
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end if;
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if write_reg_addr_111 = '1' then
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reg_addr_111_q <= reg_addr_111_d;
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end if;
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if write_reg_addr_1000 = '1' then
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reg_addr_1000_q <= reg_addr_1000_d;
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end if;
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if write_reg_addr_1001 = '1' then
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reg_addr_1001_q <= reg_addr_1001_d;
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end if;
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end if;
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end process;
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end architecture behaviour;
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