| Line 158... |
Line 158... |
assign tm_stopped = ~timer[24];
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assign tm_stopped = ~timer[24];
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assign tm_running = timer[24];
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assign tm_running = timer[24];
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assign tm_alarm = timer[25];
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assign tm_alarm = timer[25];
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reg [23:0] tm_start;
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reg [23:0] tm_start;
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reg [7:0] tm_sub;
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reg [7:0] tm_sub;
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initial tm_start = 16'h00;
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initial tm_start = 24'h00;
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initial timer = 18'h00;
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initial timer = 26'h00;
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initial tm_int = 1'b0;
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initial tm_int = 1'b0;
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initial tm_pps = 1'b0;
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initial tm_pps = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (ck_carry)
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if (ck_carry)
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| Line 249... |
Line 249... |
// will only clear it if it was already stopped.
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// will only clear it if it was already stopped.
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reg sw_pps, sw_ppm, sw_pph;
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reg sw_pps, sw_ppm, sw_pph;
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reg [7:0] sw_sub;
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reg [7:0] sw_sub;
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wire sw_running;
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wire sw_running;
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assign sw_running = stopwatch[0];
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assign sw_running = stopwatch[0];
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initial stopwatch = 32'h00001;
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initial stopwatch = 32'h00000;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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sw_pps <= 1'b0;
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sw_pps <= 1'b0;
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if (sw_running)
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if (sw_running)
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begin
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begin
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| Line 400... |
Line 400... |
// on another clock, but we'll get there.
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// on another clock, but we'll get there.
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//
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//
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reg r_hack_carry;
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reg r_hack_carry;
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reg [29:0] hack_time;
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reg [29:0] hack_time;
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reg [39:0] hack_counter;
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reg [39:0] hack_counter;
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initial hack_time = 30'h0000;
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initial hack_counter = 40'h0000;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_hack)
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if (i_hack)
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begin
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begin
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hack_time <= { clock[21:0], ck_sub };
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hack_time <= { clock[21:0], ck_sub };
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hack_counter <= ck_counter;
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hack_counter <= ck_counter;
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| Line 416... |
Line 418... |
hack_time <= { clock[21:0], ck_sub };
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hack_time <= { clock[21:0], ck_sub };
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r_hack_carry <= 1'b0;
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r_hack_carry <= 1'b0;
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end
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end
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reg [15:0] h_sseg;
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reg [15:0] h_sseg;
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reg [3:0] dmask;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(clock[27:24])
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case(clock[27:24])
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4'h0: h_sseg <= { 2'b00, ck_last_clock[21:8] };
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4'h1: begin h_sseg <= timer[15:0];
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4'h1: h_sseg <= timer[15:0];
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if (tm_alarm) dmask <= 4'hf;
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4'h2: h_sseg <= stopwatch[19:4];
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else begin
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4'h3: h_sseg <= ck_last_clock[15:0];
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dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
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default: h_sseg <= { 2'b00, ck_last_clock[21:8] };
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dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
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dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
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dmask[0] <= 1'b1; // Always on
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end end
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4'h2: begin h_sseg <= stopwatch[19:4];
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dmask[3] <= (12'h00 != stopwatch[27:16]);
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dmask[2] <= (16'h000 != stopwatch[27:12]);
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dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
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dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
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end
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4'h3: begin h_sseg <= ck_last_clock[15:0];
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dmask[3:0] <= 4'hf;
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end
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default: begin // 4'h0
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h_sseg <= { 2'b00, ck_last_clock[21:8] };
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dmask[2:0] <= 3'hf;
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dmask[3] <= (2'b00 != ck_last_clock[21:20]);
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end
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endcase
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endcase
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wire [31:0] w_sseg;
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wire [31:0] w_sseg;
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assign w_sseg[ 0] = (~ck_sub[7]);
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assign w_sseg[ 0] = (~ck_sub[7]);
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assign w_sseg[ 8] = 1'b0;
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assign w_sseg[ 8] = (clock[27:24] == 4'h2);
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assign w_sseg[16] = 1'b0;
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assign w_sseg[16] = ((clock[27:24] == 4'h0)&&(~ck_sub[7]))||(clock[27:24] == 4'h3);
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assign w_sseg[24] = 1'b0;
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assign w_sseg[24] = 1'b0;
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hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
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hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
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hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
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hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
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hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
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hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
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hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
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hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((tm_alarm || al_tripped)&&(ck_sub[7]))
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if ((tm_alarm || al_tripped)&&(ck_sub[7]))
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o_sseg <= 32'h0000;
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o_sseg <= 32'h0000;
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else
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else
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o_sseg <= w_sseg;
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o_sseg <= {
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(dmask[3])?w_sseg[31:24]:8'h00,
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(dmask[2])?w_sseg[23:16]:8'h00,
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(dmask[1])?w_sseg[15: 8]:8'h00,
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(dmask[0])?w_sseg[ 7: 0]:8'h00 };
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reg [17:0] ledreg;
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reg [17:0] ledreg;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if ((ck_pps)&&(ck_ppm))
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if ((ck_pps)&&(ck_ppm))
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ledreg <= 18'h00;
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ledreg <= 18'h00;
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else if (ck_carry)
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else if (ck_carry)
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ledreg <= ledreg + 18'h11;
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ledreg <= ledreg + 18'h11;
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assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:ledreg[17:2];
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assign o_led = (tm_alarm||al_tripped)?{ (16){ck_sub[7]}}:
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{ ledreg[17:10],
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ledreg[10], ledreg[11], ledreg[12], ledreg[13],
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ledreg[14], ledreg[15], ledreg[16], ledreg[17] };
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assign o_interrupt = tm_int || al_int;
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assign o_interrupt = tm_int || al_int;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr[2:0])
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case(i_wb_addr[2:0])
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3'b000: o_data <= { clock[31:22], ck_last_clock };
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3'b000: o_data <= { clock[31:22], ck_last_clock };
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3'b001: o_data <= { 14'h00, timer };
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3'b001: o_data <= { 6'h00, timer };
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3'b010: o_data <= stopwatch;
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3'b010: o_data <= stopwatch;
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3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
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3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
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3'b100: o_data <= ckspeed;
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3'b100: o_data <= ckspeed;
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3'b101: o_data <= { 2'b00, hack_time };
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3'b101: o_data <= { 2'b00, hack_time };
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3'b110: o_data <= hack_counter[39:8];
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3'b110: o_data <= hack_counter[39:8];
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