| Line 47... |
Line 47... |
o_sseg, o_led, o_interrupt,
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o_sseg, o_led, o_interrupt,
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// A once-per-day strobe on the last clock of the day
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// A once-per-day strobe on the last clock of the day
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o_ppd,
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o_ppd,
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// Time setting hack(s)
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// Time setting hack(s)
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i_hack);
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i_hack);
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parameter DEFAULT_SPEED = 32'd2814750; //2af31e = 2^48 / 100e6 MHz
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [2:0] i_wb_addr;
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input [2:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// input i_btn;
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// input i_btn;
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| Line 58... |
Line 59... |
output reg [31:0] o_sseg;
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output reg [31:0] o_sseg;
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output wire [15:0] o_led;
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output wire [15:0] o_led;
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output wire o_interrupt, o_ppd;
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output wire o_interrupt, o_ppd;
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input i_hack;
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input i_hack;
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|
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reg [31:0] clock, stopwatch, ckspeed;
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reg [31:0] stopwatch, ckspeed;
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reg [25:0] timer;
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reg [25:0] clock, timer;
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|
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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| Line 76... |
Line 77... |
{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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|
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wire ck_pps;
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wire ck_pps;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg [7:0] ck_sub;
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reg [7:0] ck_sub;
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initial clock = 32'h00000000;
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initial clock = 26'h000000;
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assign ck_pps = (ck_carry)&&(ck_prepps);
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assign ck_pps = (ck_carry)&&(ck_prepps);
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (ck_carry)
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if (ck_carry)
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ck_sub <= ck_sub + 1;
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ck_sub <= ck_sub + 8'h1;
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ck_prepps <= (ck_sub == 8'hff);
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ck_prepps <= (ck_sub == 8'hff);
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|
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if (ck_pps)
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if (ck_pps)
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begin // advance the seconds
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begin // advance the seconds
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if (clock[3:0] >= 4'h9)
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if (clock[3:0] >= 4'h9)
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| Line 141... |
Line 142... |
clock[15:8] <= i_wb_data[15:8];
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clock[15:8] <= i_wb_data[15:8];
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ck_pph <= (i_wb_data[15:8] == 8'h59);
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ck_pph <= (i_wb_data[15:8] == 8'h59);
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end
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end
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if (6'h3f != i_wb_data[21:16])
|
if (6'h3f != i_wb_data[21:16])
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clock[21:16] <= i_wb_data[21:16];
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clock[21:16] <= i_wb_data[21:16];
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clock[31:22] <= i_wb_data[31:22];
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clock[25:22] <= i_wb_data[25:22];
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if (8'h00 == i_wb_data[7:0])
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if (8'h00 == i_wb_data[7:0])
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ck_sub <= 8'h00;
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ck_sub <= 8'h00;
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end
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end
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end
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end
|
|
|
| Line 169... |
Line 170... |
initial tm_pps = 1'b0;
|
initial tm_pps = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
|
begin
|
if (ck_carry)
|
if (ck_carry)
|
begin
|
begin
|
tm_sub <= tm_sub + 1;
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tm_sub <= tm_sub + 8'h1;
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tm_pps <= (tm_sub == 8'hff);
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tm_pps <= (tm_sub == 8'hff);
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end else
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end else
|
tm_pps <= 1'b0;
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tm_pps <= 1'b0;
|
|
|
if ((~tm_alarm)&&(tm_running)&&(tm_pps))
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if ((~tm_alarm)&&(tm_running)&&(tm_pps))
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| Line 260... |
Line 261... |
sw_pps <= 1'b0;
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sw_pps <= 1'b0;
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if (sw_running)
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if (sw_running)
|
begin
|
begin
|
if (ck_carry)
|
if (ck_carry)
|
begin
|
begin
|
sw_sub <= sw_sub + 1;
|
sw_sub <= sw_sub + 8'h1;
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sw_pps <= (sw_sub == 8'hff);
|
sw_pps <= (sw_sub == 8'hff);
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end
|
end
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end
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end
|
|
|
stopwatch[7:1] <= sw_sub[7:1];
|
stopwatch[7:1] <= sw_sub[7:1];
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| Line 378... |
Line 379... |
// real time clock RTL file can handle tracking the clock in any
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// real time clock RTL file can handle tracking the clock in any
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// device. Further, because this is only the lower 32 bits of a
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// device. Further, because this is only the lower 32 bits of a
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// 48 bit counter per seconds, the clock jitter is kept below
|
// 48 bit counter per seconds, the clock jitter is kept below
|
// 1 part in 65 thousand.
|
// 1 part in 65 thousand.
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//
|
//
|
initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz
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initial ckspeed = DEFAULT_SPEED;
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// In the case of verilator, comment the above and uncomment the line
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// In the case of verilator, comment the above and uncomment the line
|
// below. The clock constant below is "close" to simulation time,
|
// below. The clock constant below is "close" to simulation time,
|
// meaning that my verilator simulation is running about 300x slower
|
// meaning that my verilator simulation is running about 300x slower
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// than board time.
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// than board time.
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// initial ckspeed = 32'd786432000;
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// initial ckspeed = 32'd786432000;
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| Line 423... |
Line 424... |
end
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end
|
|
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reg [15:0] h_sseg;
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reg [15:0] h_sseg;
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reg [3:1] dmask;
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reg [3:1] dmask;
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(clock[27:24])
|
case(clock[25:24])
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4'h1: begin h_sseg <= timer[15:0];
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2'h1: begin h_sseg <= timer[15:0];
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if (tm_alarm) dmask <= 3'h7;
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if (tm_alarm) dmask <= 3'h7;
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else begin
|
else begin
|
dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
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dmask[3] <= (12'h000 != timer[23:12]); // timer[15:12]
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dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
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dmask[2] <= (16'h000 != timer[23: 8]); // timer[11: 8]
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dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
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dmask[1] <= (20'h000 != timer[23: 4]); // timer[ 7: 4]
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// dmask[0] <= 1'b1; // Always on
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// dmask[0] <= 1'b1; // Always on
|
end end
|
end end
|
4'h2: begin h_sseg <= stopwatch[19:4];
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2'h2: begin h_sseg <= stopwatch[19:4];
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dmask[3] <= (12'h00 != stopwatch[27:16]);
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dmask[3] <= (12'h00 != stopwatch[27:16]);
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dmask[2] <= (16'h000 != stopwatch[27:12]);
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dmask[2] <= (16'h000 != stopwatch[27:12]);
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dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
|
dmask[1] <= 1'b1; // Always on, stopwatch[11:8]
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// dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
|
// dmask[0] <= 1'b1; // Always on, stopwatch[7:4]
|
end
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end
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4'h3: begin h_sseg <= ck_last_clock[15:0];
|
2'h3: begin h_sseg <= ck_last_clock[15:0];
|
dmask[3:1] <= 3'h7;
|
dmask[3:1] <= 3'h7;
|
end
|
end
|
default: begin // 4'h0
|
default: begin // 4'h0
|
h_sseg <= { 2'b00, ck_last_clock[21:8] };
|
h_sseg <= { 2'b00, ck_last_clock[21:8] };
|
dmask[2:1] <= 2'b11;
|
dmask[2:1] <= 2'b11;
|
| Line 450... |
Line 451... |
end
|
end
|
endcase
|
endcase
|
|
|
wire [31:0] w_sseg;
|
wire [31:0] w_sseg;
|
assign w_sseg[ 0] = (~ck_sub[7]);
|
assign w_sseg[ 0] = (~ck_sub[7]);
|
assign w_sseg[ 8] = (clock[27:24] == 4'h2);
|
assign w_sseg[ 8] = (clock[25:24] == 2'h2);
|
assign w_sseg[16] = ((clock[27:24] == 4'h0)&&(~ck_sub[7]))||(clock[27:24] == 4'h3);
|
assign w_sseg[16] = ((clock[25:24] == 2'h0)&&(~ck_sub[7]))||(clock[25:24] == 2'h3);
|
assign w_sseg[24] = 1'b0;
|
assign w_sseg[24] = 1'b0;
|
hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
|
hexmap ha(i_clk, h_sseg[ 3: 0], w_sseg[ 7: 1]);
|
hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
|
hexmap hb(i_clk, h_sseg[ 7: 4], w_sseg[15: 9]);
|
hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
|
hexmap hc(i_clk, h_sseg[11: 8], w_sseg[23:17]);
|
hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
|
hexmap hd(i_clk, h_sseg[15:12], w_sseg[31:25]);
|
| Line 488... |
Line 489... |
// connecting this module to a year/month/date date/calendar module.
|
// connecting this module to a year/month/date date/calendar module.
|
assign o_ppd = (ck_ppd)&&(ck_pps);
|
assign o_ppd = (ck_ppd)&&(ck_pps);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
case(i_wb_addr[2:0])
|
case(i_wb_addr[2:0])
|
3'b000: o_data <= { clock[31:22], ck_last_clock };
|
3'b000: o_data <= { 6'h00, clock[25:22], ck_last_clock };
|
3'b001: o_data <= { 6'h00, timer };
|
3'b001: o_data <= { 6'h00, timer };
|
3'b010: o_data <= stopwatch;
|
3'b010: o_data <= stopwatch;
|
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
|
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
|
3'b100: o_data <= ckspeed;
|
3'b100: o_data <= ckspeed;
|
3'b101: o_data <= { 2'b00, hack_time };
|
3'b101: o_data <= { 2'b00, hack_time };
|
