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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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module rtcclock(i_clk,
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module rtclight(i_clk,
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// Wishbone interface
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// Wishbone interface
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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// o_wb_ack, o_wb_stb, o_wb_data, // no reads here
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// o_wb_ack, o_wb_stb, o_wb_data, // no reads here
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// // Button inputs
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// // Button inputs
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// i_btn,
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// i_btn,
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Line 50... |
o_data, // multiplexed based upon i_wb_addr
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o_data, // multiplexed based upon i_wb_addr
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// Output controls
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// Output controls
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o_interrupt,
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o_interrupt,
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// A once-per-day strobe on the last clock of the day
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// A once-per-day strobe on the last clock of the day
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o_ppd);
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o_ppd);
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parameter DEFAULT_SPEED = 32'd2814750;
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input i_clk;
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input i_clk;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [2:0] i_wb_addr;
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input [2:0] i_wb_addr;
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input [31:0] i_wb_data;
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input [31:0] i_wb_data;
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// input i_btn;
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// input i_btn;
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output reg [31:0] o_data;
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output reg [31:0] o_data;
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output wire o_interrupt, o_ppd;
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output wire o_interrupt, o_ppd;
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reg [31:0] clock, stopwatch, ckspeed;
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reg [21:0] clock;
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reg [31:0] stopwatch, ckspeed;
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reg [25:0] timer;
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reg [25:0] timer;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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wire ck_sel, tm_sel, sw_sel, sp_sel, al_sel;
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assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign ck_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b000));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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wire ck_pps;
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wire ck_pps;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg [7:0] ck_sub;
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reg [7:0] ck_sub;
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initial clock = 32'h00000000;
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initial clock = 22'h00000;
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assign ck_pps = (ck_carry)&&(ck_prepps);
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assign ck_pps = (ck_carry)&&(ck_prepps);
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (ck_carry)
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if (ck_carry)
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ck_sub <= ck_sub + 8'h1;
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ck_sub <= ck_sub + 8'h1;
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clock[15:8] <= i_wb_data[15:8];
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clock[15:8] <= i_wb_data[15:8];
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ck_pph <= (i_wb_data[15:8] == 8'h59);
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ck_pph <= (i_wb_data[15:8] == 8'h59);
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end
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end
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if (6'h3f != i_wb_data[21:16])
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if (6'h3f != i_wb_data[21:16])
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clock[21:16] <= i_wb_data[21:16];
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clock[21:16] <= i_wb_data[21:16];
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clock[31:22] <= i_wb_data[31:22];
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if (8'h00 == i_wb_data[7:0])
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if (8'h00 == i_wb_data[7:0])
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ck_sub <= 8'h00;
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ck_sub <= 8'h00;
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end
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end
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end
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end
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// real time clock RTL file can handle tracking the clock in any
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// real time clock RTL file can handle tracking the clock in any
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// device. Further, because this is only the lower 32 bits of a
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// device. Further, because this is only the lower 32 bits of a
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// 48 bit counter per seconds, the clock jitter is kept below
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// 48 bit counter per seconds, the clock jitter is kept below
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// 1 part in 65 thousand.
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// 1 part in 65 thousand.
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//
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//
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initial ckspeed = 32'd2814750; // 2af31e = 2^48 / 100e6 MHz
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initial ckspeed = DEFAULT_SPEED; // 2af31e = 2^48 / 100e6 MHz
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// In the case of verilator, comment the above and uncomment the line
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// In the case of verilator, comment the above and uncomment the line
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// below. The clock constant below is "close" to simulation time,
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// below. The clock constant below is "close" to simulation time,
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// meaning that my verilator simulation is running about 300x slower
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// meaning that my verilator simulation is running about 300x slower
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// than board time.
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// than board time.
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// initial ckspeed = 32'd786432000;
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// initial ckspeed = 32'd786432000;
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// connecting this module to a year/month/date date/calendar module.
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// connecting this module to a year/month/date date/calendar module.
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assign o_ppd = (ck_ppd)&&(ck_pps);
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assign o_ppd = (ck_ppd)&&(ck_pps);
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always @(posedge i_clk)
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always @(posedge i_clk)
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case(i_wb_addr[2:0])
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case(i_wb_addr[2:0])
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3'b000: o_data <= { clock[31:22], ck_last_clock };
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3'b000: o_data <= { 10'h0, ck_last_clock };
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3'b001: o_data <= { 6'h00, timer };
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3'b001: o_data <= { 6'h00, timer };
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3'b010: o_data <= stopwatch;
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3'b010: o_data <= stopwatch;
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3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
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3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
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3'b100: o_data <= ckspeed;
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3'b100: o_data <= ckspeed;
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default: o_data <= 32'h000;
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default: o_data <= 32'h000;
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