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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//=============================================================================
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//=============================================================================
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// (C) 2013 Robert Finch
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// (C) 2013 Robert Finch
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// All rights reserved.
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// All rights reserved.
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// robfinch@Opencores.org
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// robfinch<remove>@Opencores.org
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//
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//
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// RTF65002PIC.v
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// RTF65002PIC.v
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//
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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//
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//
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// 3 - write only
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// 3 - write only
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// this register enables the interrupt indicated
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// this register enables the interrupt indicated
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// by the low order four bits of the input data
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// by the low order four bits of the input data
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//
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//
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// 4 - write only
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// this register indicates which interrupt inputs are
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// edge sensitive
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//
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// 5 - write only
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// This register resets the edge sense circuitry
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// indicated by the low order four bits of the input data.
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//
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// |WISHBONE Datasheet
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// |WISHBONE Datasheet
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |WISHBONE SoC Architecture Specification, Revision B.3
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// |
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// |
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// |Description: Specifications:
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// |Description: Specifications:
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parameter pIOAddress = 32'hFFDC_0FF0;
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parameter pIOAddress = 32'hFFDC_0FF0;
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reg [15:0] ie; // interrupt enable register
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reg [15:0] ie; // interrupt enable register
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reg ack1;
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reg ack1;
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reg [3:0] irqenc;
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reg [3:0] irqenc;
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wire [15:0] i = {i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,nmii};
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reg [15:0] ib;
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reg [15:0] iedge;
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reg [15:0] rste;
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reg [15:0] es;
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wire cs = cyc_i && stb_i && adr_i[33:6]==pIOAddress[31:4];
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wire cs = cyc_i && stb_i && adr_i[33:6]==pIOAddress[31:4];
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assign vol_o = cs;
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assign vol_o = cs;
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always @(posedge clk_i)
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always @(posedge clk_i)
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ack1 <= cs;
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ack1 <= cs;
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assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;
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assign ack_o = cs ? (we_i ? 1'b1 : ack1) : 1'b0;
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// write registers
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// write registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (rst_i)
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if (rst_i) begin
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ie <= 16'h0;
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ie <= 16'h0;
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else if (cs & we_i)
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rste <= 16'h0;
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case (adr_i[3:2])
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end
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2'd0,2'd1:
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else begin
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rste <= 16'h0;
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if (cs & we_i) begin
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case (adr_i[4:2])
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3'd0,3'd1:
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begin
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begin
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ie[15:0] <= dat_i[15:0];
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ie[15:0] <= dat_i[15:0];
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end
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end
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2'd2,2'd3:
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3'd2,3'd3:
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ie[dat_i[3:0]] <= adr_i[2];
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ie[dat_i[3:0]] <= adr_i[2];
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3'd4: es <= dat_i[15:0];
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3'd5: rste[dat_i[3:0]] <= 1'b1;
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endcase
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endcase
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end
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end
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// read registers
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// read registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (irqenc!=4'd0)
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if (irqenc!=4'd0)
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end
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end
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assign irqo = irqenc != 4'h0;
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assign irqo = irqenc != 4'h0;
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assign nmio = nmii & ie[0];
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assign nmio = nmii & ie[0];
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// irq requests are latched on every clock edge to prevent
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// Edge detect circuit
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integer n;
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always @(posedge clk_i)
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begin
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for (n = 1; n < 16; n = n + 1)
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begin
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ib[n] <= i[n];
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if (i[n] & !ib[n]) iedge[n] <= 1'b1;
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if (rste[n]) iedge[n] <= 1'b0;
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end
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end
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// irq requests are latched on every rising clock edge to prevent
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// misreads
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// misreads
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// nmi is not encoded
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// nmi is not encoded
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always @(posedge clk_i)
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always @(posedge clk_i)
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case (1'b1)
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begin
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i1&ie[1]: irqenc <= 4'd1;
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irqenc <= 4'd0;
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i2&ie[2]: irqenc <= 4'd2;
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for (n = 15; n > 0; n = n - 1)
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i3&ie[3]: irqenc <= 4'd3;
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if (ie[n] & (es[n] ? iedge[n] : i[n])) irqenc <= n;
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i4&ie[4]: irqenc <= 4'd4;
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end
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i5&ie[5]: irqenc <= 4'd5;
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i6&ie[6]: irqenc <= 4'd6;
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i7&ie[7]: irqenc <= 4'd7;
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i8&ie[8]: irqenc <= 4'd8;
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i9&ie[9]: irqenc <= 4'd9;
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i10&ie[10]: irqenc <= 4'd10;
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i11&ie[11]: irqenc <= 4'd11;
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i12&ie[12]: irqenc <= 4'd12;
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i13&ie[13]: irqenc <= 4'd13;
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i14&ie[14]: irqenc <= 4'd14;
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i15&ie[15]: irqenc <= 4'd15;
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default: irqenc <= 4'd0;
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endcase
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assign vecno = pVECNO|irqenc;
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assign vecno = pVECNO|irqenc;
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endmodule
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endmodule
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