| Line 22... |
Line 22... |
// ============================================================================
|
// ============================================================================
|
//
|
//
|
BYTE_DECODE:
|
BYTE_DECODE:
|
begin
|
begin
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
state <= IFETCH;
|
state <= BYTE_IFETCH;
|
|
pc <= pc + pc_inc8;
|
case(ir[7:0])
|
case(ir[7:0])
|
`STP: begin clk_en <= 1'b0; pc <= pc + 32'd1; end
|
`STP: begin clk_en <= 1'b0; end
|
`NAT: begin em <= 1'b0; pc <= pc + 32'd1; end
|
`NAT: begin em <= 1'b0; state <= IFETCH; end
|
`NOP: pc <= pc + 32'd1;
|
`NOP: ;
|
`CLC: begin cf <= 1'b0; pc <= pc + 32'd1; end
|
`CLC: begin cf <= 1'b0; end
|
`SEC: begin cf <= 1'b1; pc <= pc + 32'd1; end
|
`SEC: begin cf <= 1'b1; end
|
`CLV: begin vf <= 1'b0; pc <= pc + 32'd1; end
|
`CLV: begin vf <= 1'b0; end
|
`CLI: begin im <= 1'b0; pc <= pc + 32'd1; end
|
`CLI: begin im <= 1'b0; end
|
`SEI: begin im <= 1'b1; pc <= pc + 32'd1; end
|
`SEI: begin im <= 1'b1; end
|
`CLD: begin df <= 1'b0; pc <= pc + 32'd1; end
|
`CLD: begin df <= 1'b0; end
|
`SED: begin df <= 1'b1; pc <= pc + 32'd1; end
|
`SED: begin df <= 1'b1; end
|
`WAI: begin wai <= 1'b1; pc <= pc + 32'd1; end
|
`WAI: begin wai <= 1'b1; end
|
`DEX: begin res8 <= x[7:0] - 8'd1; pc <= pc + 32'd1; end
|
`DEX: begin res8 <= x[7:0] - 8'd1; end
|
`INX: begin res8 <= x[7:0] + 8'd1; pc <= pc + 32'd1; end
|
`INX: begin res8 <= x[7:0] + 8'd1; end
|
`DEY: begin res8 <= y[7:0] - 8'd1; pc <= pc + 32'd1; end
|
`DEY: begin res8 <= y[7:0] - 8'd1; end
|
`INY: begin res8 <= y[7:0] + 8'd1; pc <= pc + 32'd1; end
|
`INY: begin res8 <= y[7:0] + 8'd1; end
|
`DEA: begin res8 <= acc[7:0] - 8'd1; pc <= pc + 32'd1; end
|
`DEA: begin res8 <= acc[7:0] - 8'd1; end
|
`INA: begin res8 <= acc[7:0] + 8'd1; pc <= pc + 32'd1; end
|
`INA: begin res8 <= acc[7:0] + 8'd1; end
|
`TSX,`TSA: begin res8 <= sp[7:0]; pc <= pc + 32'd1; end
|
`TSX,`TSA: begin res8 <= sp[7:0]; end
|
`TXS,`TXA,`TXY: begin res8 <= x[7:0]; pc <= pc + 32'd1; end
|
`TXS,`TXA,`TXY: begin res8 <= x[7:0]; end
|
`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; pc <= pc + 32'd1; end
|
`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; end
|
`TYA,`TYX: begin res8 <= y[7:0]; pc <= pc + 32'd1; end
|
`TYA,`TYX: begin res8 <= y[7:0]; end
|
`ASL_ACC: begin res8 <= {acc8,1'b0}; pc <= pc + 32'd1; end
|
`ASL_ACC: begin res8 <= {acc8,1'b0}; end
|
`ROL_ACC: begin res8 <= {acc8,cf}; pc <= pc + 32'd1; end
|
`ROL_ACC: begin res8 <= {acc8,cf}; end
|
`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; pc <= pc + 32'd1; end
|
`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; end
|
`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; pc <= pc + 32'd1; end
|
`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; end
|
// Handle # mode
|
// Handle # mode
|
`LDA_IMM,`LDX_IMM,`LDY_IMM:
|
`LDA_IMM,`LDX_IMM,`LDY_IMM:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
res8 <= ir[15:8];
|
res8 <= ir[15:8];
|
end
|
end
|
`ADC_IMM:
|
`ADC_IMM:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 + ir[15:8] + {7'b0,cf};
|
res8 <= acc8 + ir[15:8] + {7'b0,cf};
|
b8 <= ir[15:8]; // for overflow calc
|
b8 <= ir[15:8]; // for overflow calc
|
end
|
end
|
`SBC_IMM:
|
`SBC_IMM:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
// res8 <= acc8 - ir[15:8] - ~cf;
|
// res8 <= acc8 - ir[15:8] - ~cf;
|
res8 <= acc8 - ir[15:8] - {7'b0,~cf};
|
res8 <= acc8 - ir[15:8] - {7'b0,~cf};
|
$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
|
$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
|
b8 <= ir[15:8]; // for overflow calc
|
b8 <= ir[15:8]; // for overflow calc
|
end
|
end
|
`AND_IMM,`BIT_IMM:
|
`AND_IMM,`BIT_IMM:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 & ir[15:8];
|
res8 <= acc8 & ir[15:8];
|
b8 <= ir[15:8]; // for bit flags
|
b8 <= ir[15:8]; // for bit flags
|
end
|
end
|
`ORA_IMM:
|
`ORA_IMM: res8 <= acc8 | ir[15:8];
|
begin
|
`EOR_IMM: res8 <= acc8 ^ ir[15:8];
|
pc <= pc + 32'd2;
|
`CMP_IMM: res8 <= acc8 - ir[15:8];
|
res8 <= acc8 | ir[15:8];
|
`CPX_IMM: res8 <= x8 - ir[15:8];
|
end
|
`CPY_IMM: res8 <= y8 - ir[15:8];
|
`EOR_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 ^ ir[15:8];
|
|
end
|
|
`CMP_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= acc8 - ir[15:8];
|
|
end
|
|
`CPX_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= x8 - ir[15:8];
|
|
end
|
|
`CPY_IMM:
|
|
begin
|
|
pc <= pc + 32'd2;
|
|
res8 <= y8 - ir[15:8];
|
|
end
|
|
// Handle zp mode
|
// Handle zp mode
|
`LDX_ZP,`LDY_ZP,`LDA_ZP:
|
`LDX_ZP,`LDY_ZP,`LDA_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
|
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
|
`BIT_ZP,`CPX_ZP,`CPY_ZP,
|
`BIT_ZP,`CPX_ZP,`CPY_ZP,
|
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
|
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ZP:
|
`STA_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
wadr <= zp_address[31:2];
|
wadr2LSB <= zp_address[1:0];
|
wadr2LSB <= zp_address[1:0];
|
wdat <= {4{acc8}};
|
store_what <= `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ZP:
|
`STX_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
wadr <= zp_address[31:2];
|
wadr2LSB <= zp_address[1:0];
|
wadr2LSB <= zp_address[1:0];
|
wdat <= {4{x8}};
|
store_what <= `STW_X8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ZP:
|
`STY_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
wadr <= zp_address[31:2];
|
wadr2LSB <= zp_address[1:0];
|
wadr2LSB <= zp_address[1:0];
|
wdat <= {4{y8}};
|
store_what <= `STW_Y8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ZP:
|
`STZ_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zp_address[31:2];
|
wadr <= zp_address[31:2];
|
wadr2LSB <= zp_address[1:0];
|
wadr2LSB <= zp_address[1:0];
|
wdat <= {4{8'h00}};
|
store_what <= `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle zp,x mode
|
// Handle zp,x mode
|
`LDY_ZPX,`LDA_ZPX:
|
`LDY_ZPX,`LDA_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
|
radr2LSB <= zpx_address[1:0];
|
radr2LSB <= zpx_address[1:0];
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
|
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
|
`BIT_ZPX,
|
`BIT_ZPX,
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
|
radr2LSB <= zpx_address[1:0];
|
radr2LSB <= zpx_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ZPX:
|
`STA_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
wadr <= zpx_address[31:2];
|
wadr2LSB <= zpx_address[1:0];
|
wadr2LSB <= zpx_address[1:0];
|
wdat <= {4{acc8}};
|
store_what <= `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ZPX:
|
`STY_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
wadr <= zpx_address[31:2];
|
wadr2LSB <= zpx_address[1:0];
|
wadr2LSB <= zpx_address[1:0];
|
wdat <= {4{y8}};
|
store_what <= `STW_Y8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ZPX:
|
`STZ_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zpx_address[31:2];
|
wadr <= zpx_address[31:2];
|
wadr2LSB <= zpx_address[1:0];
|
wadr2LSB <= zpx_address[1:0];
|
wdat <= {4{8'h00}};
|
store_what <= `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle zp,y
|
// Handle zp,y
|
`LDX_ZPY:
|
`LDX_ZPY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zpy_address[31:2];
|
radr <= zpy_address[31:2];
|
radr2LSB <= zpy_address[1:0];
|
radr2LSB <= zpy_address[1:0];
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STX_ZPY:
|
`STX_ZPY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
wadr <= zpy_address[31:2];
|
wadr <= zpy_address[31:2];
|
wadr2LSB <= zpy_address[1:0];
|
wadr2LSB <= zpy_address[1:0];
|
wdat <= {4{x8}};
|
store_what <= `STW_X8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle (zp,x)
|
// Handle (zp,x)
|
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
|
radr2LSB <= zpx_address[1:0];
|
radr2LSB <= zpx_address[1:0];
|
load_what <= `IA_70;
|
load_what <= `IA_70;
|
|
store_what <= `STW_ACC8;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle (zp),y
|
// Handle (zp),y
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
isIY <= `TRUE;
|
isIY <= `TRUE;
|
load_what <= `IA_70;
|
load_what <= `IA_70;
|
|
store_what <= `STW_ACC8;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle abs
|
// Handle abs
|
`LDA_ABS,`LDX_ABS,`LDY_ABS:
|
`LDA_ABS,`LDX_ABS,`LDY_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
`CPX_ABS,`CPY_ABS,
|
`CPX_ABS,`CPY_ABS,
|
`BIT_ABS:
|
`BIT_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABS:
|
`STA_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{acc8}};
|
store_what <= `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ABS:
|
`STX_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{x8}};
|
store_what <= `STW_X8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ABS:
|
`STY_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{y8}};
|
store_what <= `STW_Y8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ABS:
|
`STZ_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
wdat <= {4{8'h00}};
|
store_what <= `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle abs,x
|
// Handle abs,x
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
`LDY_ABSX:
|
`LDY_ABSX:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
radr <= absx_address[31:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSX:
|
`STA_ABSX:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= absx_address[31:2];
|
wadr <= absx_address[31:2];
|
wadr2LSB <= absx_address[1:0];
|
wadr2LSB <= absx_address[1:0];
|
wdat <= {4{acc8}};
|
store_what <= `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ABSX:
|
`STZ_ABSX:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= absx_address[31:2];
|
wadr <= absx_address[31:2];
|
wadr2LSB <= absx_address[1:0];
|
wadr2LSB <= absx_address[1:0];
|
wdat <= {4{8'h00}};
|
store_what <= `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle abs,y
|
// Handle abs,y
|
`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
|
`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
|
`LDX_ABSY:
|
`LDX_ABSY:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
radr <= absy_address[31:2];
|
radr <= absy_address[31:2];
|
radr2LSB <= absy_address[1:0];
|
radr2LSB <= absy_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSY:
|
`STA_ABSY:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
|
wadr <= absy_address[31:2];
|
wadr <= absy_address[31:2];
|
wadr2LSB <= absy_address[1:0];
|
wadr2LSB <= absy_address[1:0];
|
wdat <= {4{acc8}};
|
store_what <= `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle (zp)
|
// Handle (zp)
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
load_what <= `IA_70;
|
load_what <= `IA_70;
|
|
store_what <= `STW_ACC8;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BRK:
|
`BRK:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wdat <= {4{pcp2[31:24]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[31:24]}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
vect <= `BYTE_IRQ_VECT;
|
store_what <= `STW_PC3124;
|
state <= BYTE_IRQ1;
|
state <= STORE1;
|
bf <= 1'b1;
|
bf <= !hwi;
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc[15:0] <= abs_address[15:0];
|
pc[15:0] <= abs_address[15:0];
|
end
|
end
|
| Line 387... |
Line 329... |
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wdat <= {4{pcp2[15:8]}};
|
store_what <= `STW_PC158;
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[15:8]}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= BYTE_JSR1;
|
state <= STORE1;
|
end
|
end
|
`JSL:
|
`JSL:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wdat <= {4{pcp4[31:24]}};
|
store_what <= `STW_PC3124;
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp4[31:24]}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= BYTE_JSL1;
|
state <= STORE1;
|
end
|
end
|
`JSR_INDX:
|
`JSR_INDX:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
wdat <= {4{pcp2[15:8]}};
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
case(sp_dec[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{pcp2[15:8]}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= BYTE_JSR_INDX1;
|
store_what <= `STW_PC158;
|
|
state <= STORE1;
|
end
|
end
|
`RTS,`RTL:
|
`RTS,`RTL:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
| Line 461... |
Line 370... |
load_what <= `SR_70;
|
load_what <= `SR_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
begin
|
begin
|
// if (ir[15:8]==8'hFE) begin
|
|
// radr <= {24'h1,sp[7:2]};
|
|
// radr2LSB <= sp[1:0];
|
|
// wadr <= {24'h1,sp[7:2]};
|
|
// wadr2LSB <= sp[1:0];
|
|
// case(sp[1:0])
|
|
// 2'd0: sel_o <= 4'b0001;
|
|
// 2'd1: sel_o <= 4'b0010;
|
|
// 2'd2: sel_o <= 4'b0100;
|
|
// 2'd3: sel_o <= 4'b1000;
|
|
// endcase
|
|
// wdat <= {4{pcp2[31:24]}};
|
|
// cyc_o <= 1'b1;
|
|
// stb_o <= 1'b1;
|
|
// we_o <= 1'b1;
|
|
// adr_o <= {24'h1,sp[7:2],2'b00};
|
|
// dat_o <= {4{pcp2[31:24]}};
|
|
// vect <= `SLP_VECT;
|
|
// state <= BYTE_IRQ1;
|
|
// end
|
|
// else
|
|
if (ir[15:8]==8'hFF) begin
|
if (ir[15:8]==8'hFF) begin
|
if (takb)
|
if (takb)
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
else
|
else
|
pc <= pc + 32'd4;
|
pc <= pc + 32'd4;
|
end
|
end
|
else begin
|
else
|
|
begin
|
if (takb)
|
if (takb)
|
pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
|
pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
|
else
|
else
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
end
|
end
|
end
|
end
|
`PHP:
|
`PHP:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
case(sp[1:0])
|
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{sr8}};
|
|
wdat <= {4{sr8}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= STORE2;
|
store_what <= `STW_SR70;
|
pc <= pc + 32'd1;
|
state <= STORE1;
|
end
|
end
|
`PHA:
|
`PHA:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
case(sp[1:0])
|
store_what <= `STW_ACC8;
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{acc8}};
|
|
wdat <= {4{acc8}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= STORE2;
|
state <= STORE1;
|
pc <= pc + 32'd1;
|
|
end
|
end
|
`PHX:
|
`PHX:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
case(sp[1:0])
|
store_what <= `STW_X8;
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{x8}};
|
|
wdat <= {4{x8}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
state <= STORE2;
|
state <= STORE1;
|
pc <= pc + 32'd1;
|
|
end
|
end
|
`PHY:
|
`PHY:
|
begin
|
begin
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr2LSB <= sp[1:0];
|
wadr2LSB <= sp[1:0];
|
case(sp[1:0])
|
store_what <= `STW_Y8;
|
2'd0: sel_o <= 4'b0001;
|
|
2'd1: sel_o <= 4'b0010;
|
|
2'd2: sel_o <= 4'b0100;
|
|
2'd3: sel_o <= 4'b1000;
|
|
endcase
|
|
adr_o <= {spage[31:8],sp[7:2],2'b00};
|
|
dat_o <= {4{y8}};
|
|
wdat <= {4{y8}};
|
|
sp <= sp_dec;
|
sp <= sp_dec;
|
pc <= pc + 32'd1;
|
state <= STORE1;
|
state <= STORE2;
|
|
end
|
end
|
`PLP:
|
`PLP:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
load_what <= `SR_70;
|
load_what <= `SR_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
pc <= pc + 32'd1;
|
|
end
|
end
|
`PLA,`PLX,`PLY:
|
`PLA,`PLX,`PLY:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
pc <= pc + 32'd1;
|
|
end
|
end
|
default: // unimplemented opcode
|
default: // unimplemented opcode
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
endcase
|
endcase
|
end
|
end
|
