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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 21 and 30

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Rev 21	Rev 30
Line 25...	Line 25...
`//`	`//`
`case(cstate)`	`case(cstate)`
`IDLE:`	`IDLE:`
`begin`	`begin`
`if (!cyc_o) begin`	`if (!cyc_o) begin`
	`ifdef SUPPORT_DCACHE
`// A write to a cacheable address does not cause a cache load`	`// A write to a cacheable address does not cause a cache load`
`if (dmiss) begin`	`if (dmiss) begin`
isDataCacheLoad <= `TRUE;	isDataCacheLoad <= `TRUE;
`if (isRMW)`	`if (isRMW)`
`lock_o <= 1'b1;`	`lock_o <= 1'b1;`
Line 38...	Line 39...
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
`adr_o <= {radr[31:2],4'h0};`	`adr_o <= {radr[31:2],4'h0};`
`cstate <= LOAD_DCACHE;`	`cstate <= LOAD_DCACHE;`
`end`	`end`
`else if (!unCachedInsn && imiss && !hit0) begin`	`else`
	`endif
	`ifdef SUPPORT_ICACHE
	`if (!unCachedInsn && imiss && !hit0) begin`
isInsnCacheLoad <= `TRUE;	isInsnCacheLoad <= `TRUE;
`bte_o <= 2'b00;`	`bte_o <= 2'b00;`
`cti_o <= 3'd001;`	`cti_o <= 3'd001;`
`bl_o <= 6'd3;`	`bl_o <= 6'd3;`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
Line 60...	Line 64...
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
`adr_o <= {pcp8[31:4],4'h0};`	`adr_o <= {pcp8[31:4],4'h0};`
`cstate <= LOAD_ICACHE;`	`cstate <= LOAD_ICACHE;`
`end`	`end`
`else if (unCachedInsn && imiss) begin`	`else`
	`endif
	`if (unCachedInsn && imiss) begin`
`bte_o <= 2'b00;`	`bte_o <= 2'b00;`
`cti_o <= 3'b001;`	`cti_o <= 3'b001;`
`bl_o <= 6'd2;`	`bl_o <= 6'd2;`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
Line 72...	Line 78...
`adr_o <= {pc[31:2],2'b00};`	`adr_o <= {pc[31:2],2'b00};`
`cstate <= LOAD_IBUF1;`	`cstate <= LOAD_IBUF1;`
`end`	`end`
`end`	`end`
`end`	`end`
	`ifdef SUPPORT_DCACHE
`LOAD_DCACHE:`	`LOAD_DCACHE:`
`if (ack_i) begin`	`if (ack_i) begin`
`if (adr_o[3:2]==2'b11) begin`	`if (adr_o[3:2]==2'b11) begin`
dmiss <= `FALSE;	dmiss <= `FALSE;
isDataCacheLoad <= `FALSE;	isDataCacheLoad <= `FALSE;
Line 88...	Line 95...
`cstate <= IDLE;`	`cstate <= IDLE;`
`end`	`end`
`adr_o <= adr_o + 34'd4;`	`adr_o <= adr_o + 34'd4;`
`end`	`end`
`// What to do here`	`// What to do here`
	`ifdef SUPPORT_BERR
`else if (err_i) begin`	`else if (err_i) begin`
`if (adr_o[3:2]==2'b11) begin`	`if (adr_o[3:2]==2'b11) begin`
dmiss <= `FALSE;	dmiss <= `FALSE;
isDataCacheLoad <= `FALSE;	isDataCacheLoad <= `FALSE;
`cti_o <= 3'b000;`	`cti_o <= 3'b000;`
Line 105...	Line 113...
`// Override the next state and send the processor to the bus error state.`	`// Override the next state and send the processor to the bus error state.`
`state <= BUS_ERROR;`	`state <= BUS_ERROR;`
`end`	`end`
`adr_o <= adr_o + 34'd4;`	`adr_o <= adr_o + 34'd4;`
`end`	`end`
	`endif
	`endif
	`ifdef SUPPORT_ICACHE
`LOAD_ICACHE:`	`LOAD_ICACHE:`
`if (ack_i) begin`	`if (ack_i) begin`
`if (adr_o[3:2]==2'b11) begin`	`if (adr_o[3:2]==2'b11) begin`
imiss <= `FALSE;	imiss <= `FALSE;
isInsnCacheLoad <= `FALSE;	isInsnCacheLoad <= `FALSE;
Line 120...	Line 131...
`adr_o <= 34'd0;`	`adr_o <= 34'd0;`
`cstate <= IDLE;`	`cstate <= IDLE;`
`end`	`end`
`adr_o <= adr_o + 34'd4;`	`adr_o <= adr_o + 34'd4;`
`end`	`end`
	`ifdef SUPPORT_BERR
`else if (err_i) begin`	`else if (err_i) begin`
`if (adr_o[3:2]==2'b11) begin`	`if (adr_o[3:2]==2'b11) begin`
imiss <= `FALSE;	imiss <= `FALSE;
isInsnCacheLoad <= `FALSE;	isInsnCacheLoad <= `FALSE;
`cti_o <= 3'b000;`	`cti_o <= 3'b000;`
Line 135...	Line 147...
`state <= INSN_BUS_ERROR;`	`state <= INSN_BUS_ERROR;`
`cstate <= IDLE;`	`cstate <= IDLE;`
`end`	`end`
`adr_o <= adr_o + 34'd4;`	`adr_o <= adr_o + 34'd4;`
`end`	`end`
	`endif
	`endif
`LOAD_IBUF1:`	`LOAD_IBUF1:`
`if (ack_i\|err_i) begin`	`if (ack_i\|err_i) begin`
`case(pc[1:0])`	`case(pc[1:0])`
`2'd0: ibuf <= dat_i;`	`2'd0: ibuf <= dat_i;`
`2'd1: ibuf <= dat_i[31:8];`	`2'd1: ibuf <= dat_i[31:8];`
Line 175...	Line 189...
`adr_o <= 34'd0;`	`adr_o <= 34'd0;`
`cstate <= IDLE;`	`cstate <= IDLE;`
imiss <= `FALSE;	imiss <= `FALSE;
`bufadr <= pc; // clears the miss`	`bufadr <= pc; // clears the miss`
`end`	`end`
	`ifdef SUPPORT_BERR
`else if (err_i) begin`	`else if (err_i) begin`
`case(pc[1:0])`	`case(pc[1:0])`
`2'd0: ;`	`2'd0: ;`
`2'd1: ;`	`2'd1: ;`
`2'd2: ibuf[55:48] <= dat_i[7:0];`	`2'd2: ibuf[55:48] <= dat_i[7:0];`
Line 193...	Line 208...
`cstate <= IDLE;`	`cstate <= IDLE;`
`state <= INSN_BUS_ERROR;`	`state <= INSN_BUS_ERROR;`
imiss <= `FALSE;	imiss <= `FALSE;
`bufadr <= pc; // clears the miss`	`bufadr <= pc; // clears the miss`
`end`	`end`
	`endif

`endcase`	`endcase`

`No newline at end of file`	`No newline at end of file`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 21 and 30