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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Diff between revs 21 and 23

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Rev 21 Rev 23
Line 41... Line 41...
                `INX:   begin res <= x + 32'd1; pc <= pc + 32'd1; end
                `INX:   begin res <= x + 32'd1; pc <= pc + 32'd1; end
                `DEY:   begin res <= y - 32'd1; pc <= pc + 32'd1; end
                `DEY:   begin res <= y - 32'd1; pc <= pc + 32'd1; end
                `INY:   begin res <= y + 32'd1; pc <= pc + 32'd1; end
                `INY:   begin res <= y + 32'd1; pc <= pc + 32'd1; end
                `DEA:   begin res <= acc - 32'd1; pc <= pc + 32'd1; end
                `DEA:   begin res <= acc - 32'd1; pc <= pc + 32'd1; end
                `INA:   begin res <= acc + 32'd1; pc <= pc + 32'd1; end
                `INA:   begin res <= acc + 32'd1; pc <= pc + 32'd1; end
                `TSX:   begin res <= isp; pc <= pc + 32'd1; end
                `TSX,`TSA:      begin res <= isp; pc <= pc + 32'd1; end
                `TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
                `TXS,`TXA,`TXY: begin res <= x; pc <= pc + 32'd1; end
                `TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
                `TAX,`TAY,`TAS: begin res <= acc; pc <= pc + 32'd1; end
                `TYA,`TYX:      begin res <= y; pc <= pc + 32'd1; end
                `TYA,`TYX:      begin res <= y; pc <= pc + 32'd1; end
                `TRS:           begin
                `TRS:           begin
                                                res <= rfoa; pc <= pc + 32'd2; end
                                                res <= rfoa; pc <= pc + 32'd2; end
Line 59... Line 59...
                                                4'h4:   res <= tick;
                                                4'h4:   res <= tick;
                                                4'h5:   begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
                                                4'h5:   begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
                                                4'h6:   res <= dp8;
                                                4'h6:   res <= dp8;
                                                4'h7:   res <= abs8;
                                                4'h7:   res <= abs8;
                                                4'h8:   res <= {vbr[31:1],nmoi};
                                                4'h8:   res <= {vbr[31:1],nmoi};
 
                                                4'h9:   res <= derr_address;
                                                4'hE:   res <= {spage[31:8],sp};
                                                4'hE:   res <= {spage[31:8],sp};
                                                4'hF:   res <= isp;
                                                4'hF:   res <= isp;
                                                endcase
                                                endcase
                                                pc <= pc + 32'd2;
                                                pc <= pc + 32'd2;
                                        end
                                        end
Line 123... Line 124...
 
 
                `LDX_IMM32,`LDY_IMM32,`LDA_IMM32:       begin res <= ir[39:8]; pc <= pc + 32'd5; end
                `LDX_IMM32,`LDY_IMM32,`LDA_IMM32:       begin res <= ir[39:8]; pc <= pc + 32'd5; end
                `LDX_IMM16,`LDA_IMM16:  begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
                `LDX_IMM16,`LDA_IMM16:  begin res <= {{16{ir[23]}},ir[23:8]}; pc <= pc + 32'd3; end
                `LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
                `LDX_IMM8,`LDA_IMM8: begin res <= {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
 
 
 
                `SUB_SP:        begin res <= isp - {{24{ir[15]}},ir[15:8]}; pc <= pc + 32'd2; end
 
 
                `LDX_ZPX,`LDY_ZPX:
                `LDX_ZPX,`LDY_ZPX:
                        begin
                        begin
                                radr <= zpx32xy_address;
                                radr <= zpx32xy_address;
                                pc <= pc + 32'd3;
                                pc <= pc + 32'd3;
                                load_what <= `WORD_311;
                                load_what <= `WORD_311;
Line 188... Line 191...
                                wadr <= zpx32_address[31:2];
                                wadr <= zpx32_address[31:2];
                                wadr2LSB <= zpx32_address[1:0];
                                wadr2LSB <= zpx32_address[1:0];
                                pc <= pc + 32'd4;
                                pc <= pc + 32'd4;
                                state <= STORE1;
                                state <= STORE1;
                        end
                        end
 
                `ST_DSP:
 
                        begin
 
                                wadr <= {{24{ir[23]}},ir[23:16]} + isp;
 
                                wdat <= rfoa;
 
                                pc <= pc + 32'd3;
 
                                state <= STORE1;
 
                        end
                `ST_ABS:
                `ST_ABS:
                        begin
                        begin
                                wadr <= ir[47:16];
                                wadr <= ir[47:16];
                                wdat <= rfoa;
                                wdat <= rfoa;
                                pc <= pc + 32'd6;
                                pc <= pc + 32'd6;
Line 262... Line 272...
                                radr <= dp + rfoa + ir[23:12];
                                radr <= dp + rfoa + ir[23:12];
                                pc <= pc + 32'd3;
                                pc <= pc + 32'd3;
                                load_what <= `WORD_310;
                                load_what <= `WORD_310;
                                state <= LOAD_MAC1;
                                state <= LOAD_MAC1;
                        end
                        end
 
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
 
                        begin
 
                                a <= rfoa;
 
                                Rt <= ir[15:12];
 
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
 
                                pc <= pc + 32'd3;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                        end
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
                        begin
                        begin
                                a <= rfoa;
                                a <= rfoa;
                                if (ir[7:0]==`ST_IX)
                                if (ir[7:0]==`ST_IX)
                                        res <= rfoa;            // for ST_IX, Rt=0
                                        res <= rfoa;            // for ST_IX, Rt=0
Line 702... Line 721...
                                isp <= isp_inc;
                                isp <= isp_inc;
                                load_what <= `WORD_311;
                                load_what <= `WORD_311;
                                state <= LOAD_MAC1;
                                state <= LOAD_MAC1;
                                pc <= pc + 32'd2;
                                pc <= pc + 32'd2;
                        end
                        end
 
                `MVN:   state <= MVN1;
 
                `MVP:   state <= MVP1;
                default:        // unimplemented opcode
                default:        // unimplemented opcode
                        begin
                        begin
                                radr <= isp_dec;
                                radr <= isp_dec;
                                wadr <= isp_dec;
                                wadr <= isp_dec;
                                wdat <= pc + 32'd1;
                                wdat <= pc + 32'd1;

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