| Line 18... |
Line 18... |
// You should have received a copy of the GNU General Public License
|
// You should have received a copy of the GNU General Public License
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
DECODE:
|
task decode_tsk;
|
begin
|
begin
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
Rt <= 4'h0; // Default
|
Rt <= 4'h0; // Default
|
state <= IFETCH;
|
state <= IFETCH;
|
pc <= pc + pc_inc;
|
pc <= pc + pc_inc;
|
a <= rfoa;
|
a <= rfoa;
|
|
res <= alu_out;
|
|
ttrig <= tf;
|
// This case statement should include all opcodes or the opcode
|
// This case statement should include all opcodes or the opcode
|
// will end up being treated as an undefined operation.
|
// will end up being treated as an undefined operation.
|
case(ir[7:0])
|
case(ir9)
|
`STP: clk_en <= 1'b0;
|
`STP: clk_en <= 1'b0;
|
`NOP: ;
|
`NOP: ;
|
// casex(ir[63:0])
|
// casex(ir[63:0])
|
// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
|
// {`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp8;
|
// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
|
// {8'hxx,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP,`NOP}: pc <= pcp7;
|
| Line 48... |
Line 50... |
`CLI: im <= 1'b0;
|
`CLI: im <= 1'b0;
|
`CLD: df <= 1'b0;
|
`CLD: df <= 1'b0;
|
`SED: df <= 1'b1;
|
`SED: df <= 1'b1;
|
`SEI: im <= 1'b1;
|
`SEI: im <= 1'b1;
|
`WAI: wai <= 1'b1;
|
`WAI: wai <= 1'b1;
|
`EMM: em <= 1'b1;
|
`TON: tf <= 1'b1;
|
`DEX: begin
|
`TOFF: tf <= 1'b0;
|
res <= x - 32'd1;
|
`HOFF: hist_capture <= 1'b0;
|
|
`EMM: begin em <= 1'b1;
|
|
`ifdef SUPPORT_EM8
|
|
state <= BYTE_IFETCH;
|
|
`endif
|
|
end
|
|
`DEX: Rt <= 4'd2;
|
// DEX/BNE accelerator
|
// DEX/BNE accelerator
|
// if (ir[15:8]==`BNE) begin
|
// if (ir[15:8]==`BNE) begin
|
// if (x!=32'd1) begin
|
// if (x!=32'd1) begin
|
// if (ir[23:16]==8'h01)
|
// if (ir[23:16]==8'h01)
|
// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
|
// pc <= pc + {{16{ir[39]}},ir[39:24]} + 32'd1;
|
| Line 66... |
Line 74... |
// pc <= pcp5;
|
// pc <= pcp5;
|
// else
|
// else
|
// pc <= pcp3;
|
// pc <= pcp3;
|
// end
|
// end
|
// end
|
// end
|
end
|
`INX: Rt <= 4'd2;
|
`INX: res <= x + 32'd1;
|
`DEY: Rt <= 4'd3;
|
`DEY: res <= y - 32'd1;
|
`INY: Rt <= 4'd3;
|
`INY: res <= y + 32'd1;
|
`DEA: Rt <= 4'd1;
|
`DEA: res <= acc - 32'd1;
|
`INA: Rt <= 4'd1;
|
`INA: res <= acc + 32'd1;
|
`TSX: Rt <= 4'd2;
|
`TSX,`TSA: res <= isp;
|
`TSA: Rt <= 4'd1;
|
`TXS,`TXA,`TXY: res <= x;
|
`TXS: ;
|
`TAX,`TAY,`TAS: res <= acc;
|
`TXA: Rt <= 4'd1;
|
`TYA,`TYX: res <= y;
|
`TXY: Rt <= 4'd3;
|
`TRS: res <= rfoa;
|
`TAX: Rt <= 4'd2;
|
|
`TAY: Rt <= 4'd3;
|
|
`TAS: ;
|
|
`TYA: Rt <= 4'd1;
|
|
`TYX: Rt <= 4'd2;
|
|
`TRS: ;
|
`TSR: begin
|
`TSR: begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
case(ir[11:8])
|
case(ir[11:8])
|
4'h0:
|
4'h0: ;
|
begin
|
4'h2: ;
|
`ifdef SUPPORT_ICACHE
|
4'h3: ;
|
res[0] <= icacheOn;
|
4'h4: ;
|
`endif
|
4'h5: lfsr <= {lfsr[30:0],lfsr_fb};
|
`ifdef SUPPORT_DCACHE
|
4'd7: ;
|
res[1] <= dcacheOn;
|
4'h8: ;
|
res[2] <= write_allocate;
|
4'h9: ;
|
`endif
|
4'hA: history_ndx <= history_ndx + 6'd1;
|
res[31:3] <= 29'd0;
|
4'hE: ;
|
end
|
4'hF: ;
|
4'h2: res <= prod[31:0];
|
default: ;
|
4'h3: res <= prod[63:32];
|
|
4'h4: res <= tick;
|
|
4'h5: begin res <= lfsr; lfsr <= {lfsr[30:0],lfsr_fb}; end
|
|
4'h7: begin res <= history_buf[history_ndx]; history_ndx <= history_ndx + 6'd1; end// was abs8
|
|
4'h8: res <= {vbr[31:1],nmoi};
|
|
4'h9: res <= derr_address;
|
|
4'hE: res <= {spage[31:8],sp};
|
|
4'hF: res <= isp;
|
|
default: res <= 32'd0;
|
|
endcase
|
endcase
|
end
|
end
|
`ASL_ACC: begin res <= {acc,1'b0}; end
|
`ASL_ACC: Rt <= 4'd1;
|
`ROL_ACC: begin res <= {acc,cf};end
|
`ROL_ACC: Rt <= 4'd1;
|
`LSR_ACC: begin res <= {acc[0],1'b0,acc[31:1]}; end
|
`LSR_ACC: Rt <= 4'd1;
|
`ROR_ACC: begin res <= {acc[0],cf,acc[31:1]}; end
|
`ROR_ACC: Rt <= 4'd1;
|
|
|
`RR:
|
`RR:
|
begin
|
begin
|
state <= IFETCH;
|
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
case(ir[23:20])
|
case(ir[23:20])
|
`ADD_RR: begin res <= rfoa + rfob + {31'b0,df&cf}; b <= rfob; end
|
`ADD_RR: b <= rfob;
|
`SUB_RR: begin res <= rfoa - rfob - {31'b0,df&~cf&|ir[19:16]}; b <= rfob; end
|
`SUB_RR: b <= rfob;
|
`AND_RR: begin res <= rfoa & rfob; b <= rfob; end // for bit flags
|
`AND_RR: b <= rfob; // for bit flags
|
`OR_RR: begin res <= rfoa | rfob; b <= rfob; end
|
`OR_RR: b <= rfob;
|
`EOR_RR: begin res <= rfoa ^ rfob; b <= rfob; end
|
`EOR_RR: b <= rfob;
|
`MUL_RR: begin state <= MULDIV1; end
|
`MUL_RR: begin b <= rfob; state <= MULDIV1; end
|
`MULS_RR: begin state <= MULDIV1; end
|
`MULS_RR: begin b <= rfob; state <= MULDIV1; end
|
`ifdef SUPPORT_DIVMOD
|
`ifdef SUPPORT_DIVMOD
|
`DIV_RR: begin state <= MULDIV1; end
|
`DIV_RR: begin b <= rfob; state <= MULDIV1; end
|
`DIVS_RR: begin state <= MULDIV1; end
|
`DIVS_RR: begin b <= rfob; state <= MULDIV1; end
|
`MOD_RR: begin state <= MULDIV1; end
|
`MOD_RR: begin b <= rfob; state <= MULDIV1; end
|
`MODS_RR: begin state <= MULDIV1; end
|
`MODS_RR: begin b <= rfob; state <= MULDIV1; end
|
`endif
|
`endif
|
`ifdef SUPPORT_SHIFT
|
`ifdef SUPPORT_SHIFT
|
`ASL_RRR: begin b <= rfob; state <= CALC; end
|
`ASL_RRR: begin b <= rfob; state <= CALC; end
|
`LSR_RRR: begin b <= rfob; state <= CALC; end
|
`LSR_RRR: begin b <= rfob; state <= CALC; end
|
`endif
|
`endif
|
default:
|
default:
|
begin
|
begin
|
Rt <= 4'h0;
|
Rt <= 4'h0;
|
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
vect <= {vbr[31:9],9'd495,2'b00};
|
vect <= {vbr[31:9],9'd495,2'b00};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`LD_RR: begin res <= rfoa; Rt <= ir[15:12]; end
|
`LD_RR: Rt <= ir[15:12];
|
`ASL_RR: begin res <= {rfoa,1'b0}; Rt <= ir[15:12]; end
|
`ASL_RR: Rt <= ir[15:12];
|
`ROL_RR: begin res <= {rfoa,cf}; Rt <= ir[15:12]; end
|
`ROL_RR: Rt <= ir[15:12];
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`LSR_RR: begin res <= {rfoa[0],1'b0,rfoa[31:1]}; Rt <= ir[15:12]; end
|
`LSR_RR: Rt <= ir[15:12];
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`ROR_RR: begin res <= {rfoa[0],cf,rfoa[31:1]}; Rt <= ir[15:12]; end
|
`ROR_RR: Rt <= ir[15:12];
|
`DEC_RR: begin res <= rfoa - 32'd1; Rt <= ir[15:12]; end
|
`DEC_RR: Rt <= ir[15:12];
|
`INC_RR: begin res <= rfoa + 32'd1; Rt <= ir[15:12]; end
|
`INC_RR: Rt <= ir[15:12];
|
|
|
`ADD_IMM8: begin res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`SUB_IMM8: begin res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`OR_IMM8: begin res <= rfoa | {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
|
`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
|
`AND_IMM8: begin res <= rfoa & {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`ifdef SUPPORT_DIVMOD
|
`EOR_IMM8: begin res <= rfoa ^ {{24{ir[23]}},ir[23:16]}; Rt <= ir[15:12]; end
|
`DIV_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
|
`CMP_IMM8: begin res <= acc - {{24{ir[15]}},ir[15:8]}; end
|
`MOD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
|
|
`endif
|
|
`OR_IMM8: begin Rt <= ir[15:12]; end
|
|
`AND_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
|
`EOR_IMM8: begin Rt <= ir[15:12]; end
|
|
`CMP_IMM8: ;
|
`ifdef SUPPORT_SHIFT
|
`ifdef SUPPORT_SHIFT
|
`ASL_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
|
`ASL_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
|
`LSR_IMM8: begin b <= ir[20:16]; Rt <= ir[15:12]; state <= CALC; end
|
`LSR_IMM8: begin Rt <= ir[15:12]; b <= ir[20:16]; state <= CALC; end
|
|
`endif
|
|
|
|
`ADD_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`SUB_IMM16: begin Rt <= ir[15:12]; a <= rfoa; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`MUL_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
|
|
`ifdef SUPPORT_DIVMOD
|
|
`DIV_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
|
|
`MOD_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; state <= MULDIV1; end
|
`endif
|
`endif
|
`ADD_IMM16: begin res <= rfoa + {{16{ir[31]}},ir[31:16]} + {31'b0,df&cf}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
|
`OR_IMM16: begin Rt <= ir[15:12]; end
|
`SUB_IMM16: begin res <= rfoa - {{16{ir[31]}},ir[31:16]} - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
|
`AND_IMM16: begin Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
|
`OR_IMM16: begin res <= rfoa | {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
|
`EOR_IMM16: begin Rt <= ir[15:12]; end
|
`AND_IMM16: begin res <= rfoa & {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; b <= {{16{ir[31]}},ir[31:16]}; end
|
|
`EOR_IMM16: begin res <= rfoa ^ {{16{ir[31]}},ir[31:16]}; Rt <= ir[15:12]; end
|
|
|
|
`ADD_IMM32: begin res <= rfoa + ir[47:16] + {31'b0,df&cf}; Rt <= ir[15:12]; b <= ir[47:16]; end
|
`ADD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
|
`SUB_IMM32: begin res <= rfoa - ir[47:16] - {31'b0,df&~cf&|ir[15:12]}; Rt <= ir[15:12]; b <= ir[47:16]; end
|
`SUB_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
|
`OR_IMM32: begin res <= rfoa | ir[47:16]; Rt <= ir[15:12]; end
|
`MUL_IMM16: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
|
`AND_IMM32: begin res <= rfoa & ir[47:16]; Rt <= ir[15:12]; b <= ir[47:16]; end
|
`ifdef SUPPORT_DIVMOD
|
`EOR_IMM32: begin res <= rfoa ^ ir[47:16]; Rt <= ir[15:12]; end
|
`DIV_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
|
|
`MOD_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; state <= MULDIV1; end
|
|
`endif
|
|
`OR_IMM32: begin Rt <= ir[15:12]; end
|
|
`AND_IMM32: begin Rt <= ir[15:12]; b <= ir[47:16]; end
|
|
`EOR_IMM32: begin Rt <= ir[15:12]; end
|
|
|
`LDX_IMM32,`LDY_IMM32,`LDA_IMM32: res <= ir[39:8];
|
`LDA_IMM32: Rt <= 4'd1;
|
`LDX_IMM16,`LDA_IMM16: res <= {{16{ir[23]}},ir[23:8]};
|
`LDX_IMM32: Rt <= 4'd2;
|
`LDX_IMM8,`LDA_IMM8: res <= {{24{ir[15]}},ir[15:8]};
|
`LDY_IMM32: Rt <= 4'd3;
|
|
`LDA_IMM16: Rt <= 4'd1;
|
|
`LDX_IMM16: Rt <= 4'd2;
|
|
`LDA_IMM8: Rt <= 4'd1;
|
|
`LDX_IMM8: Rt <= 4'd2;
|
|
|
`SUB_SP8: res <= isp - {{24{ir[15]}},ir[15:8]};
|
`SUB_SP8: ;
|
`SUB_SP16: res <= isp - {{16{ir[23]}},ir[23:8]};
|
`SUB_SP16: ;
|
`SUB_SP32: res <= isp - ir[39:8];
|
`SUB_SP32: ;
|
|
|
`CPX_IMM32: res <= x - ir[39:8];
|
`CPX_IMM32: ;
|
`CPY_IMM32: res <= y - ir[39:8];
|
`CPY_IMM32: ;
|
|
|
`LDX_ZPX,`LDY_ZPX:
|
`LDX_ZPX:
|
|
begin
|
|
Rt <= 4'd2;
|
|
radr <= zpx32xy_address;
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`LDY_ZPX:
|
begin
|
begin
|
|
Rt <= 4'd3;
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ZPX:
|
`ORB_ZPX:
|
| Line 196... |
Line 228... |
radr <= zpx32_address[31:2];
|
radr <= zpx32_address[31:2];
|
radr2LSB <= zpx32_address[1:0];
|
radr2LSB <= zpx32_address[1:0];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDX_ABS,`LDY_ABS:
|
`LDX_ABS:
|
begin
|
begin
|
|
Rt <= 4'd2;
|
|
radr <= ir[39:8];
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`LDY_ABS:
|
|
begin
|
|
Rt <= 4'd3;
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ABS:
|
`ORB_ABS:
|
| Line 210... |
Line 250... |
radr <= ir[47:18];
|
radr <= ir[47:18];
|
radr2LSB <= ir[17:16];
|
radr2LSB <= ir[17:16];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LDX_ABSY,`LDY_ABSX:
|
`LDX_ABSY:
|
begin
|
begin
|
|
Rt <= 4'd2;
|
|
radr <= absx32xy_address;
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`LDY_ABSX:
|
|
begin
|
|
Rt <= 4'd3;
|
radr <= absx32xy_address;
|
radr <= absx32xy_address;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ORB_ABSX:
|
`ORB_ABSX:
|
| Line 293... |
Line 341... |
begin
|
begin
|
wadr <= ir[39:8];
|
wadr <= ir[39:8];
|
store_what <= `STW_Y;
|
store_what <= `STW_Y;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ADD_ZPX,`SUB_ZPX,`OR_ZPX,`AND_ZPX,`EOR_ZPX:
|
`ADD_ZPX,`SUB_ZPX,`AND_ZPX:
|
begin
|
begin
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
radr <= zpx32_address;
|
radr <= zpx32_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
// Trim a clock cycle off of loads by testing for Ra = 0.
|
|
`OR_ZPX,`EOR_ZPX:
|
|
begin
|
|
Rt <= ir[19:16];
|
|
radr <= zpx32_address;
|
|
load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`BMS_ZPX,`BMC_ZPX,`BMF_ZPX,`BMT_ZPX:
|
|
begin
|
|
radr <= zpx32xy_address + acc[31:5];
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
radr <= {{24{ir[23]}},ir[23:16]} + isp;
|
radr <= {{24{ir[23]}},ir[23:16]} + isp;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
| Line 345... |
Line 407... |
radr <= ir[31:20];
|
radr <= ir[31:20];
|
load_what <= `IA_310;
|
load_what <= `IA_310;
|
store_what <= `STW_A;
|
store_what <= `STW_A;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS:
|
`OR_ABS,`EOR_ABS:
|
|
begin
|
|
radr <= ir[47:16];
|
|
Rt <= ir[15:12];
|
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADD_ABS,`SUB_ABS,`AND_ABS:
|
begin
|
begin
|
radr <= ir[47:16];
|
radr <= ir[47:16];
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
| Line 358... |
Line 427... |
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX:
|
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
|
|
begin
|
|
radr <= ir[39:8] + acc[31:5];
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADD_ABSX,`SUB_ABSX,`AND_ABSX:
|
begin
|
begin
|
radr <= absx32_address;
|
radr <= absx32_address;
|
Rt <= ir[19:16];
|
Rt <= ir[19:16];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`OR_ABSX,`EOR_ABSX:
|
|
begin
|
|
radr <= absx32_address;
|
|
Rt <= ir[19:16];
|
|
load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX:
|
begin
|
begin
|
radr <= absx32xy_address;
|
radr <= absx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX:
|
|
begin
|
|
radr <= absx32xy_address + acc[31:5];
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
|
`CPX_ZPX:
|
`CPX_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
| Line 399... |
Line 487... |
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BRK:
|
`BRK:
|
begin
|
begin
|
bf <= !hwi;
|
bf <= !hwi;
|
|
km <= `TRUE;
|
hist_capture <= `FALSE;
|
hist_capture <= `FALSE;
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_PCHWI;
|
store_what <= `STW_PCHWI;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`INT0,`INT1:
|
`INT0,`INT1:
|
begin
|
begin
|
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
vect <= {vbr[31:9],ir[15:7],2'b00};
|
vect <= {vbr[31:9],ir[15:7],2'b00};
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
`JMP:
|
`JMP:
|
| Line 461... |
Line 551... |
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
pc <= rfoa;
|
pc <= rfoa;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSL:
|
`JSL,`JSR_INDX,`JSR_IND:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
pc <= ir[39:8];
|
pc <= ir[39:8]; // This pc assignment will be overridden later by JSR_INDX
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`BSR:
|
`BSR:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
| Line 481... |
Line 571... |
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
wdat <= pc+{31'd1,suppress_pcinc[0]};
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
pc <= pc + {{16{ir[23]}},ir[23:8]};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSR_INDX:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp-32'd1,2'b00};
|
|
dat_o <= suppress_pcinc[0] ? pc + 32'd5 : pc + 32'd2;
|
|
state <= JSR_INDX1;
|
|
end
|
|
// `JSR16:
|
|
// begin
|
|
// radr <= isp - 32'd1;
|
|
// wadr <= isp - 32'd1;
|
|
// wdat <= pc + 32'd3;
|
|
// cyc_o <= 1'b1;
|
|
// stb_o <= 1'b1;
|
|
// we_o <= 1'b1;
|
|
// sel_o <= 4'hF;
|
|
// adr_o <= {isp-32'd1,2'b00};
|
|
// dat_o <= pc + 32'd3;
|
|
// state <= JSR161;
|
|
// end
|
|
`RTS,`RTL:
|
`RTS,`RTL:
|
begin
|
begin
|
radr <= isp;
|
radr <= isp;
|
|
isp <= isp_inc;
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`RTI: begin
|
`RTI: begin
|
hist_capture <= `TRUE;
|
hist_capture <= `TRUE;
|
radr <= isp;
|
radr <= isp;
|
|
isp <= isp_inc;
|
load_what <= `SR_310;
|
load_what <= `SR_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA,
|
`BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
|
`BGT,`BGE,`BLT,`BLE,`BHI,`BLS:
|
begin
|
begin
|
state <= IFETCH;
|
|
if (ir[15:8]==8'h00) begin
|
if (ir[15:8]==8'h00) begin
|
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
| Line 545... |
Line 611... |
end
|
end
|
end
|
end
|
`BRL:
|
`BRL:
|
begin
|
begin
|
if (ir[23:8]==16'h0000) begin
|
if (ir[23:8]==16'h0000) begin
|
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
vect <= {vbr[31:9],`SLP_VECTNO,2'b00};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
| Line 560... |
Line 627... |
`ifdef SUPPORT_EXEC
|
`ifdef SUPPORT_EXEC
|
`EXEC,`ATNI:
|
`EXEC,`ATNI:
|
begin
|
begin
|
exbuf[31:0] <= rfoa;
|
exbuf[31:0] <= rfoa;
|
exbuf[63:32] <= rfob;
|
exbuf[63:32] <= rfob;
|
state <= IFETCH;
|
|
end
|
end
|
`endif
|
`endif
|
`PHP:
|
`PHP:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
| Line 599... |
Line 665... |
end
|
end
|
`PUSH:
|
`PUSH:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
|
store_what <= `STW_A;
|
|
state <= STORE1;
|
|
isp <= isp_dec;
|
|
end
|
|
`PUSHA:
|
|
begin
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
ir[11:8] <= 4'd1;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
isp <= isp_dec;
|
isp <= isp_dec;
|
end
|
end
|
`PLP:
|
`PLP:
|
begin
|
begin
|
radr <= isp;
|
radr <= isp;
|
|
isp <= isp_inc;
|
load_what <= `SR_310;
|
load_what <= `SR_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`PLA,`PLX,`PLY:
|
`PLA:
|
begin
|
begin
|
|
Rt <= 4'd1;
|
|
radr <= isp;
|
|
isp <= isp_inc;
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`PLX:
|
|
begin
|
|
Rt <= 4'd2;
|
|
radr <= isp;
|
|
isp <= isp_inc;
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`PLY:
|
|
begin
|
|
Rt <= 4'd3;
|
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
| Line 624... |
Line 717... |
radr <= isp;
|
radr <= isp;
|
isp <= isp_inc;
|
isp <= isp_inc;
|
load_what <= `WORD_311;
|
load_what <= `WORD_311;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`POPA:
|
|
begin
|
|
Rt <= 4'd15;
|
|
radr <= isp;
|
|
isp <= isp_inc;
|
|
load_what <= `WORD_311;
|
|
state <= LOAD_MAC1;
|
|
end
|
`ifdef SUPPORT_STRING
|
`ifdef SUPPORT_STRING
|
`MVN: state <= MVN1;
|
`MVN:
|
`MVP: state <= MVP1;
|
begin
|
`STS: state <= STS1;
|
Rt <= 4'd3;
|
|
radr <= x;
|
|
res <= x + 32'd1;
|
|
load_what <= `WORD_312;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`MVP:
|
|
begin
|
|
Rt <= 4'd3;
|
|
radr <= x;
|
|
res <= x - 32'd1;
|
|
load_what <= `WORD_312;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`STS:
|
|
begin
|
|
Rt <= 4'd3;
|
|
radr <= y;
|
|
wadr <= y;
|
|
store_what <= `STW_X;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
|
end
|
|
`CMPS:
|
|
begin
|
|
Rt <= 4'd3;
|
|
radr <= x;
|
|
res <= x + 32'd1;
|
|
load_what <= `WORD_313;
|
|
state <= LOAD_MAC1;
|
|
end
|
`endif
|
`endif
|
|
`PG2: begin
|
|
pg2 <= `TRUE;
|
|
ir <= ir[63:8];
|
|
state <= DECODE;
|
|
end
|
default: // unimplemented opcode
|
default: // unimplemented opcode
|
begin
|
begin
|
res <= 32'd0;
|
res <= 32'd0;
|
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
vect <= {vbr[31:9],9'd495,2'b00};
|
vect <= {vbr[31:9],9'd495,2'b00};
|
pc <= pc; // override the pc increment
|
pc <= pc; // override the pc increment
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
endtask
|
|
|
No newline at end of file
|
No newline at end of file
|
