URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 12 and 30

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 12	Rev 30
Line 21...	Line 21...
`// You should have received a copy of the GNU General Public License`	`// You should have received a copy of the GNU General Public License`
`// along with this program. If not, see <http://www.gnu.org/licenses/>.`	`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
	`define SUPPORT_DIVMOD 1'b1

`define MUL 4'd8	`define MUL 4'd8
`define MULS 4'd9	`define MULS 4'd9
`define DIV 4'd10	`define DIV 4'd10
`define DIVS 4'd11	`define DIVS 4'd11
`define MOD 4'd12	`define MOD 4'd12
Line 77...	Line 79...
`aa <= a[31] ? -a : a;`	`aa <= a[31] ? -a : a;`
`bb <= b[31] ? -b : b;`	`bb <= b[31] ? -b : b;`
`res_sgn <= a[31] ^ b[31];`	`res_sgn <= a[31] ^ b[31];`
`state <= MULT;`	`state <= MULT;`
`end`	`end`
	`ifdef SUPPORT_DIVMOD
`DIV,`MOD:	`DIV,`MOD:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
`bb <= b;`	`bb <= b;`
`q <= a[30:0];`	`q <= a[30:0];`
Line 95...	Line 98...
`q <= pa[30:0];`	`q <= pa[30:0];`
`r <= pa[31];`	`r <= pa[31];`
`res_sgn <= a[31] ^ b[31];`	`res_sgn <= a[31] ^ b[31];`
`state <= DIV;`	`state <= DIV;`
`end`	`end`
	`endif
`default:`	`default:`
`state <= IDLE;`	`state <= IDLE;`
`endcase`	`endcase`
`end`	`end`
`MULT:`	`MULT:`
`begin`	`begin`
`state <= res_sgn ? FIX_SIGN : IDLE;`	`state <= res_sgn ? FIX_SIGN : IDLE;`
`p <= aa * bb;`	`p <= aa * bb;`
`end`	`end`
	`ifdef SUPPORT_DIVMOD
`DIV:`	`DIV:`
`begin`	`begin`
`q <= {q[30:0],~diff[31]};`	`q <= {q[30:0],~diff[31]};`
`if (cnt==6'd0) begin`	`if (cnt==6'd0) begin`
`state <= res_sgn ? FIX_SIGN : IDLE;`	`state <= res_sgn ? FIX_SIGN : IDLE;`
Line 122...	Line 127...
`else`	`else`
`r <= {diff[30:0],q[31]};`	`r <= {diff[30:0],q[31]};`
`end`	`end`
`cnt <= cnt - 6'd1;`	`cnt <= cnt - 6'd1;`
`end`	`end`
	`endif

`FIX_SIGN:`	`FIX_SIGN:`
`begin`	`begin`
`state <= IDLE;`	`state <= IDLE;`
`if (res_sgn) begin`	`if (res_sgn) begin`

Browse

Tools

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 12 and 30