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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 30 and 32

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`// You should have received a copy of the GNU General Public License`	`// You should have received a copy of the GNU General Public License`
`// along with this program. If not, see <http://www.gnu.org/licenses/>.`	`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
`//`	`//`
`// ============================================================================`	`// ============================================================================`
`//`	`//`
`define SUPPORT_DIVMOD 1'b1	`include "rtf65002_defines.v"

`define MUL 4'd8	`module mult_div(rst, clk, ld, op, fn, a, b, p, q, r, done);`
`define MULS 4'd9
`define DIV 4'd10
`define DIVS 4'd11
`define MOD 4'd12
`define MODS 4'd13

`module mult_div(rst, clk, ld, op, a, b, p, q, r, done);`
`parameter IDLE=3'd0;`	`parameter IDLE=3'd0;`
`parameter MULT=3'd1;`	`parameter MULT=3'd1;`
`parameter FIX_SIGN=3'd2;`	`parameter FIX_SIGN=3'd2;`
`parameter DIV=3'd3;`	`parameter DIV=3'd3;`
`input rst;`	`input rst;`
`input clk;`	`input clk;`
`input ld;`	`input ld;`
`input [3:0] op;`	`input [8:0] op;`
	`input [3:0] fn;`
`input [31:0] a;`	`input [31:0] a;`
`input [31:0] b;`	`input [31:0] b;`
`output reg [63:0] p;`	`output reg [63:0] p;`
`output reg [31:0] q;`	`output reg [31:0] q;`
`output reg [31:0] r;`	`output reg [31:0] r;`
Line 65...	Line 59...
`case(state)`	`case(state)`
`IDLE:`	`IDLE:`
`if (ld) begin`	`if (ld) begin`
`cnt <= 6'd32;`	`cnt <= 6'd32;`
`case(op)`	`case(op)`
`MUL:	`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
	`begin`
	`aa <= a;`
	`bb <= b;`
	`res_sgn <= 1'b0;`
	`state <= MULT;`
	`end`
	`ifdef SUPPORT_DIVMOD
	`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
	`MOD_IMM8,`MOD_IMM16,`MOD_IMM32:
	`begin`
	`aa <= a;`
	`bb <= b;`
	`q <= a[30:0];`
	`r <= a[31];`
	`res_sgn <= 1'b0;`
	`state <= DIV;`
	`end`
	`endif
	`RR:
	`case(fn)`
	`MUL_RR:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
`bb <= b;`	`bb <= b;`
`res_sgn <= 1'b0;`	`res_sgn <= 1'b0;`
`state <= MULT;`	`state <= MULT;`
`end`	`end`
`MULS:	`MULS_RR:
`begin`	`begin`
`aa <= a[31] ? -a : a;`	`aa <= a[31] ? -a : a;`
`bb <= b[31] ? -b : b;`	`bb <= b[31] ? -b : b;`
`res_sgn <= a[31] ^ b[31];`	`res_sgn <= a[31] ^ b[31];`
`state <= MULT;`	`state <= MULT;`
`end`	`end`
`ifdef SUPPORT_DIVMOD	`ifdef SUPPORT_DIVMOD
`DIV,`MOD:	`DIV_RR,`MOD_RR:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
`bb <= b;`	`bb <= b;`
`q <= a[30:0];`	`q <= a[30:0];`
`r <= a[31];`	`r <= a[31];`
`res_sgn <= 1'b0;`	`res_sgn <= 1'b0;`
`state <= DIV;`	`state <= DIV;`
`end`	`end`
`DIVS,`MODS:	`DIVS_RR,`MODS_RR:
`begin`	`begin`
`aa <= a[31] ? -a : a;`	`aa <= a[31] ? -a : a;`
`bb <= b[31] ? -b : b;`	`bb <= b[31] ? -b : b;`
`q <= pa[30:0];`	`q <= pa[30:0];`
`r <= pa[31];`	`r <= pa[31];`
Line 102...	Line 117...
`end`	`end`
`endif	`endif
`default:`	`default:`
`state <= IDLE;`	`state <= IDLE;`
`endcase`	`endcase`
	`endcase`
`end`	`end`
`MULT:`	`MULT:`
`begin`	`begin`
`state <= res_sgn ? FIX_SIGN : IDLE;`	`state <= res_sgn ? FIX_SIGN : IDLE;`
`p <= aa * bb;`	`p <= aa * bb;`
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`mult_div umd1 (`	`mult_div umd1 (`
`.rst(rst),`	`.rst(rst),`
`.clk(clk),`	`.clk(clk),`
`.ld(ld),`	`.ld(ld),`
.op(`DIV),	.op(`RR),
	.fn(`DIV_RR),
`.a(32'h12345678),`	`.a(32'h12345678),`
`.b(32'd10),`	`.b(32'd10),`
`.p(),`	`.p(),`
`.q(),`	`.q(),`
`.r(),`	`.r(),`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 30 and 32