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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_dtagmem.v] - Diff between revs 30 and 32
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| Rev 30 |
Rev 32 |
| Line 18... |
Line 18... |
// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module rtf65002_dtagmem(wclk, wr, wadr, rclk, radr, hit);
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module rtf65002_dtagmem(wclk, wr, wadr, cr, rclk, radr, hit);
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [31:0] wadr;
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input [31:0] wadr;
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input cr;
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input rclk;
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input rclk;
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input [31:0] radr;
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input [31:0] radr;
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output hit;
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output hit;
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reg [31:0] rradr;
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reg [31:0] rradr;
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Line 37... |
.wrst(1'b0),
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.wrst(1'b0),
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.wclk(wclk),
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.wclk(wclk),
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.wce(wadr[1:0]==2'b11),
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.wce(wadr[1:0]==2'b11),
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.we(wr),
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.we(wr),
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.wadr(wadr[10:2]),
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.wadr(wadr[10:2]),
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.i(wadr),
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.i({wadr[31:1],cr}),
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.wo(),
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.wo(),
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.rrst(1'b0),
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.rrst(1'b0),
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.rclk(rclk),
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.rclk(rclk),
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.rce(1'b1),
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.rce(1'b1),
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.radr(radr[10:2]),
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.radr(radr[10:2]),
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always @(posedge rclk)
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always @(posedge rclk)
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rradr <= radr;
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rradr <= radr;
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assign hit = tag[31:11]==rradr[31:11];
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assign hit = tag[31:11]==rradr[31:11] && tag[0];
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endmodule
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endmodule
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