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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`define TRUE 1'b1
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`include "rtf65002_defines.v"
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`define FALSE 1'b0
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`define RST_VECT 34'h3FFFFFFF8
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`define NMI_VECT 34'h3FFFFFFF4
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`define IRQ_VECT 34'h3FFFFFFF0
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`define BRK_VECTNO 9'd0
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`define SLP_VECTNO 9'd1
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`define BYTE_RST_VECT 34'h00000FFFC
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`define BYTE_NMI_VECT 34'h00000FFFA
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`define BYTE_IRQ_VECT 34'h00000FFFE
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`define BRK 8'h00
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`define RTI 8'h40
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`define RTS 8'h60
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`define PHP 8'h08
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`define CLC 8'h18
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`define PLP 8'h28
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`define SEC 8'h38
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`define PHA 8'h48
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`define CLI 8'h58
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`define PLA 8'h68
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`define SEI 8'h78
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`define DEY 8'h88
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`define TYA 8'h98
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`define TAY 8'hA8
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`define CLV 8'hB8
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`define INY 8'hC8
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`define CLD 8'hD8
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`define INX 8'hE8
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`define SED 8'hF8
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`define ROR_ACC 8'h6A
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`define TXA 8'h8A
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`define TXS 8'h9A
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`define TAX 8'hAA
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`define TSX 8'hBA
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`define DEX 8'hCA
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`define NOP 8'hEA
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`define TXY 8'h9B
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`define TYX 8'hBB
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`define TAS 8'h1B
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`define TSA 8'h3B
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`define TRS 8'h8B
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`define TSR 8'hAB
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`define STP 8'hDB
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`define NAT 8'hFB
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`define EMM 8'hFB
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`define INA 8'h1A
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`define DEA 8'h3A
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`define RR 8'h02
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`define ADD_RR 4'd0
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`define SUB_RR 4'd1
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`define CMP_RR 4'd2
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`define AND_RR 4'd3
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`define EOR_RR 4'd4
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`define OR_RR 4'd5
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`define MUL_RR 4'd8
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`define MULS_RR 4'd9
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`define DIV_RR 4'd10
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`define DIVS_RR 4'd11
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`define MOD_RR 4'd12
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`define MODS_RR 4'd13
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`define ASL_RRR 4'd14
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`define LSR_RRR 4'd15
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`define LD_RR 8'h7B
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`define ADD_IMM8 8'h65 // 8 bit operand
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`define ADD_IMM16 8'h79 // 16 bit operand
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`define ADD_IMM32 8'h69 // 32 bit operand
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`define ADD_ZPX 8'h75 // there is no ZP mode, use R0 to syntheisze
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`define ADD_IX 8'h61
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`define ADD_IY 8'h71
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`define ADD_ABS 8'h6D
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`define ADD_ABSX 8'h7D
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`define ADD_RIND 8'h72
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`define ADD_DSP 8'h63
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`define SUB_IMM8 8'hE5
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`define SUB_IMM16 8'hF9
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`define SUB_IMM32 8'hE9
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`define SUB_ZPX 8'hF5
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`define SUB_IX 8'hE1
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`define SUB_IY 8'hF1
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`define SUB_ABS 8'hED
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`define SUB_ABSX 8'hFD
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`define SUB_RIND 8'hF2
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`define SUB_DSP 8'hE3
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// CMP = SUB r0,....
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`define ADC_IMM 8'h69
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`define ADC_ZP 8'h65
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`define ADC_ZPX 8'h75
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`define ADC_IX 8'h61
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`define ADC_IY 8'h71
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`define ADC_ABS 8'h6D
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`define ADC_ABSX 8'h7D
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`define ADC_ABSY 8'h79
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`define ADC_I 8'h72
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`define SBC_IMM 8'hE9
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`define SBC_ZP 8'hE5
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`define SBC_ZPX 8'hF5
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`define SBC_IX 8'hE1
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`define SBC_IY 8'hF1
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`define SBC_ABS 8'hED
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`define SBC_ABSX 8'hFD
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`define SBC_ABSY 8'hF9
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`define SBC_I 8'hF2
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`define CMP_IMM8 8'hC5
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`define CMP_IMM32 8'hC9
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`define CMP_IMM 8'hC9
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`define CMP_ZP 8'hC5
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`define CMP_ZPX 8'hD5
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`define CMP_IX 8'hC1
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`define CMP_IY 8'hD1
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`define CMP_ABS 8'hCD
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`define CMP_ABSX 8'hDD
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`define CMP_ABSY 8'hD9
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`define CMP_I 8'hD2
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`define LDA_IMM8 8'hA5
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`define LDA_IMM16 8'hB9
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`define LDA_IMM32 8'hA9
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`define AND_IMM8 8'h25
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`define AND_IMM16 8'h39
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`define AND_IMM32 8'h29
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`define AND_IMM 8'h29
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`define AND_ZP 8'h25
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`define AND_ZPX 8'h35
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`define AND_IX 8'h21
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`define AND_IY 8'h31
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`define AND_ABS 8'h2D
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`define AND_ABSX 8'h3D
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`define AND_ABSY 8'h39
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`define AND_RIND 8'h32
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`define AND_I 8'h32
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`define AND_DSP 8'h23
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`define OR_IMM8 8'h05
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`define OR_IMM16 8'h19
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`define OR_IMM32 8'h09
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`define OR_ZPX 8'h15
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`define OR_IX 8'h01
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`define OR_IY 8'h11
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`define OR_ABS 8'h0D
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`define OR_ABSX 8'h1D
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`define OR_RIND 8'h12
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`define OR_DSP 8'h03
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`define ORA_IMM 8'h09
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`define ORA_ZP 8'h05
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`define ORA_ZPX 8'h15
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`define ORA_IX 8'h01
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`define ORA_IY 8'h11
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`define ORA_ABS 8'h0D
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`define ORA_ABSX 8'h1D
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`define ORA_ABSY 8'h19
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`define ORA_I 8'h12
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`define EOR_IMM 8'h49
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`define EOR_IMM8 8'h45
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`define EOR_IMM16 8'h59
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`define EOR_IMM32 8'h49
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`define EOR_ZP 8'h45
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`define EOR_ZPX 8'h55
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`define EOR_IX 8'h41
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`define EOR_IY 8'h51
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`define EOR_ABS 8'h4D
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`define EOR_ABSX 8'h5D
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`define EOR_ABSY 8'h59
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`define EOR_RIND 8'h52
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`define EOR_I 8'h52
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`define EOR_DSP 8'h43
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// LD is OR rt,r0,....
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`define ST_ZPX 8'h95
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`define ST_IX 8'h81
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`define ST_IY 8'h91
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`define ST_ABS 8'h8D
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`define ST_ABSX 8'h9D
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`define ST_RIND 8'h92
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`define ST_DSP 8'h83
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`define ORB_ZPX 8'hB5
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`define ORB_IX 8'hA1
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`define ORB_IY 8'hB1
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`define ORB_ABS 8'hAD
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`define ORB_ABSX 8'hBD
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`define STB_ZPX 8'h74
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`define STB_ABS 8'h9C
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`define STB_ABSX 8'h9E
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//`define LDB_RIND 8'hB2 // Conflict with LDX #imm16
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`define LDA_IMM 8'hA9
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`define LDA_ZP 8'hA5
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`define LDA_ZPX 8'hB5
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`define LDA_IX 8'hA1
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`define LDA_IY 8'hB1
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`define LDA_ABS 8'hAD
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`define LDA_ABSX 8'hBD
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`define LDA_ABSY 8'hB9
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`define LDA_I 8'hB2
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`define STA_ZP 8'h85
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`define STA_ZPX 8'h95
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`define STA_IX 8'h81
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`define STA_IY 8'h91
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`define STA_ABS 8'h8D
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`define STA_ABSX 8'h9D
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`define STA_ABSY 8'h99
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`define STA_I 8'h92
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`define ASL_IMM8 8'h24
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`define ASL_ACC 8'h0A
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`define ASL_ZP 8'h06
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`define ASL_RR 8'h06
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`define ASL_ZPX 8'h16
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`define ASL_ABS 8'h0E
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`define ASL_ABSX 8'h1E
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`define ROL_ACC 8'h2A
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`define ROL_ZP 8'h26
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`define ROL_RR 8'h26
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`define ROL_ZPX 8'h36
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`define ROL_ABS 8'h2E
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`define ROL_ABSX 8'h3E
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`define LSR_IMM8 8'h34
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`define LSR_ACC 8'h4A
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`define LSR_ZP 8'h46
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`define LSR_RR 8'h46
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`define LSR_ZPX 8'h56
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`define LSR_ABS 8'h4E
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`define LSR_ABSX 8'h5E
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`define ROR_RR 8'h66
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`define ROR_ZP 8'h66
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`define ROR_ZPX 8'h76
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`define ROR_ABS 8'h6E
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`define ROR_ABSX 8'h7E
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`define DEC_RR 8'hC6
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`define DEC_ZP 8'hC6
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`define DEC_ZPX 8'hD6
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`define DEC_ABS 8'hCE
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`define DEC_ABSX 8'hDE
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`define INC_RR 8'hE6
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`define INC_ZP 8'hE6
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`define INC_ZPX 8'hF6
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`define INC_ABS 8'hEE
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`define INC_ABSX 8'hFE
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`define BIT_IMM 8'h89
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`define BIT_ZP 8'h24
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`define BIT_ZPX 8'h34
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`define BIT_ABS 8'h2C
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`define BIT_ABSX 8'h3C
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// CMP = SUB r0,...
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// BIT = AND r0,...
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`define BPL 8'h10
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`define BVC 8'h50
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`define BCC 8'h90
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`define BNE 8'hD0
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`define BMI 8'h30
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`define BVS 8'h70
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`define BCS 8'hB0
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`define BEQ 8'hF0
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`define BRL 8'h82
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`define BRA 8'h80
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`define JML 8'h5C
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`define JMP 8'h4C
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`define JMP_IND 8'h6C
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`define JMP_INDX 8'h7C
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`define JMP_RIND 8'hD2
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`define JSR 8'h20
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`define JSL 8'h22
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`define JSR_INDX 8'hFC
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`define JSR_RIND 8'hC2
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`define RTS 8'h60
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`define RTL 8'h6B
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`define BSR 8'h62
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`define NOP 8'hEA
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`define BRK 8'h00
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`define PLX 8'hFA
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`define PLY 8'h7A
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`define PHX 8'hDA
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`define PHY 8'h5A
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`define WAI 8'hCB
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`define PUSH 8'h0B
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`define POP 8'h2B
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`define LDX_IMM 8'hA2
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`define LDX_ZP 8'hA6
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`define LDX_ZPX 8'hB6
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`define LDX_ZPY 8'hB6
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`define LDX_ABS 8'hAE
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`define LDX_ABSY 8'hBE
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`define LDX_IMM32 8'hA2
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`define LDX_IMM16 8'hB2
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`define LDX_IMM8 8'hA6
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`define LDY_IMM 8'hA0
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`define LDY_ZP 8'hA4
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`define LDY_ZPX 8'hB4
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`define LDY_IMM32 8'hA0
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`define LDY_ABS 8'hAC
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`define LDY_ABSX 8'hBC
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`define STX_ZP 8'h86
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`define STX_ZPX 8'h96
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`define STX_ZPY 8'h96
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`define STX_ABS 8'h8E
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`define STY_ZP 8'h84
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`define STY_ZPX 8'h94
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`define STY_ABS 8'h8C
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`define STZ_ZP 8'h64
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`define STZ_ZPX 8'h74
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`define STZ_ABS 8'h9C
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`define STZ_ABSX 8'h9E
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`define CPX_IMM 8'hE0
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`define CPX_IMM32 8'hE0
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`define CPX_ZP 8'hE4
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`define CPX_ZPX 8'hE4
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`define CPX_ABS 8'hEC
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`define CPY_IMM 8'hC0
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`define CPY_IMM32 8'hC0
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`define CPY_ZP 8'hC4
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`define CPY_ZPX 8'hC4
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`define CPY_ABS 8'hCC
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`define TRB_ZP 8'h14
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`define TRB_ZPX 8'h14
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`define TRB_ABS 8'h1C
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`define TSB_ZP 8'h04
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`define TSB_ZPX 8'h04
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`define TSB_ABS 8'h0C
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`define BAZ 8'hC1
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`define BXZ 8'hD1
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`define BEQ_RR 8'hE2
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`define INT0 8'hDC
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`define INT1 8'hDD
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`define SUB_SP8 8'h85
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`define SUB_SP16 8'h99
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`define SUB_SP32 8'h89
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`define MVP 8'h44
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`define MVN 8'h54
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`define EXEC 8'hEB
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`define ATNI 8'h4B
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`define NOTHING 4'd0
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`define SR_70 4'd1
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`define SR_310 4'd2
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`define BYTE_70 4'd3
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`define WORD_310 4'd4
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`define PC_70 4'd5
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`define PC_158 4'd6
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`define PC_2316 4'd7
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`define PC_3124 4'd8
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`define PC_310 4'd9
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`define WORD_311 4'd10
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`define IA_310 4'd11
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`define IA_70 4'd12
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`define IA_158 4'd13
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`define BYTE_71 4'd14
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`define WORD_312 4'd15
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module icachemem(wclk, wr, adr, dat, rclk, pc, insn);
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input wclk;
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input wr;
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input [33:0] adr;
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input [31:0] dat;
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input rclk;
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input [31:0] pc;
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output reg [63:0] insn;
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wire [63:0] insn0;
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wire [63:0] insn1;
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wire [31:0] pcp8 = pc + 32'd8;
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reg [31:0] rpc;
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always @(posedge rclk)
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rpc <= pc;
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// memL and memH combined allow a 64 bit read
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syncRam2kx32_1rw1r ramL0
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(
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.wrst(1'b0),
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.wclk(wclk),
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.wce(~adr[2]),
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.we(wr),
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.wsel(4'hF),
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.wadr(adr[13:3]),
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.i(dat),
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.wo(),
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.rrst(1'b0),
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.rclk(rclk),
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.rce(1'b1),
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.radr(pc[13:3]),
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.o(insn0[31:0])
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);
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syncRam2kx32_1rw1r ramH0
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(
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.wrst(1'b0),
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.wclk(wclk),
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.wce(adr[2]),
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.we(wr),
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.wsel(4'hF),
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.wadr(adr[13:3]),
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.i(dat),
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.wo(),
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.rrst(1'b0),
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.rclk(rclk),
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.rce(1'b1),
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.radr(pc[13:3]),
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.o(insn0[63:32])
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);
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syncRam2kx32_1rw1r ramL1
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(
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.wrst(1'b0),
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.wclk(wclk),
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.wce(~adr[2]),
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.we(wr),
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.wsel(4'hF),
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.wadr(adr[13:3]),
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.i(dat),
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.wo(),
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.rrst(1'b0),
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.rclk(rclk),
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.rce(1'b1),
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.radr(pcp8[13:3]),
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.o(insn1[31:0])
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);
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syncRam2kx32_1rw1r ramH1
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(
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.wrst(1'b0),
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.wclk(wclk),
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.wce(adr[2]),
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.we(wr),
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.wsel(4'hF),
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.wadr(adr[13:3]),
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.i(dat),
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.wo(),
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.rrst(1'b0),
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.rclk(rclk),
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.rce(1'b1),
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.radr(pcp8[13:3]),
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.o(insn1[63:32])
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);
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always @(rpc or insn0 or insn1)
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case(rpc[2:0])
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3'd0: insn <= insn0[63:0];
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3'd1: insn <= {insn1[7:0],insn0[63:8]};
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3'd2: insn <= {insn1[15:0],insn0[63:16]};
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3'd3: insn <= {insn1[23:0],insn0[63:24]};
|
|
3'd4: insn <= {insn1[31:0],insn0[63:32]};
|
|
3'd5: insn <= {insn1[39:0],insn0[63:40]};
|
|
3'd6: insn <= {insn1[47:0],insn0[63:48]};
|
|
3'd7: insn <= {insn1[55:0],insn0[63:56]};
|
|
endcase
|
|
endmodule
|
|
|
|
module tagmem(wclk, wr, adr, rclk, pc, hit0, hit1);
|
|
input wclk;
|
|
input wr;
|
|
input [33:0] adr;
|
|
input rclk;
|
|
input [31:0] pc;
|
|
output hit0;
|
|
output hit1;
|
|
|
|
wire [31:0] pcp8 = pc + 32'd8;
|
|
wire [31:0] tag0;
|
|
wire [31:0] tag1;
|
|
reg [31:0] rpc;
|
|
reg [31:0] rpcp8;
|
|
|
|
always @(posedge rclk)
|
|
rpc <= pc;
|
|
always @(posedge rclk)
|
|
rpcp8 <= pcp8;
|
|
|
|
syncRam1kx32_1rw1r ram0 (
|
|
.wrst(1'b0),
|
|
.wclk(wclk),
|
|
.wce(adr[3:2]==2'b11),
|
|
.we(wr),
|
|
.wsel(4'hF),
|
|
.wadr(adr[13:4]),
|
|
.i(adr[31:0]),
|
|
.wo(),
|
|
|
|
.rrst(1'b0),
|
|
.rclk(rclk),
|
|
.rce(1'b1),
|
|
.radr(pc[13:4]),
|
|
.o(tag0)
|
|
);
|
|
|
|
syncRam1kx32_1rw1r ram1 (
|
|
.wrst(1'b0),
|
|
.wclk(wclk),
|
|
.wce(adr[3:2]==2'b11),
|
|
.we(wr),
|
|
.wsel(4'hF),
|
|
.wadr(adr[13:4]),
|
|
.i(adr[31:0]),
|
|
.wo(),
|
|
|
|
.rrst(1'b0),
|
|
.rclk(rclk),
|
|
.rce(1'b1),
|
|
.radr(pcp8[13:4]),
|
|
.o(tag1)
|
|
);
|
|
|
|
assign hit0 = tag0[31:14]==rpc[31:14] && tag0[0];
|
|
assign hit1 = tag1[31:14]==rpcp8[31:14] && tag1[0];
|
|
|
|
endmodule
|
|
|
|
module dcachemem(wclk, wr, sel, wadr, wdat, rclk, radr, rdat);
|
|
input wclk;
|
|
input wr;
|
|
input [3:0] sel;
|
|
input [31:0] wadr;
|
|
input [31:0] wdat;
|
|
input rclk;
|
|
input [31:0] radr;
|
|
output [31:0] rdat;
|
|
|
|
syncRam2kx32_1rw1r ram0 (
|
|
.wrst(1'b0),
|
|
.wclk(wclk),
|
|
.wce(1'b1),
|
|
.we(wr),
|
|
.wsel(sel),
|
|
.wadr(wadr[10:0]),
|
|
.i(wdat),
|
|
.wo(),
|
|
.rrst(1'b0),
|
|
.rclk(rclk),
|
|
.rce(1'b1),
|
|
.radr(radr[10:0]),
|
|
.o(rdat)
|
|
);
|
|
|
|
endmodule
|
|
|
|
module dtagmem(wclk, wr, wadr, rclk, radr, hit);
|
|
input wclk;
|
|
input wr;
|
|
input [31:0] wadr;
|
|
input rclk;
|
|
input [31:0] radr;
|
|
output hit;
|
|
|
|
reg [31:0] rradr;
|
|
wire [31:0] tag;
|
|
|
|
syncRam512x32_1rw1r u1
|
|
(
|
|
.wrst(1'b0),
|
|
.wclk(wclk),
|
|
.wce(wadr[1:0]==2'b11),
|
|
.we(wr),
|
|
.wadr(wadr[10:2]),
|
|
.i(wadr),
|
|
.wo(),
|
|
.rrst(1'b0),
|
|
.rclk(rclk),
|
|
.rce(1'b1),
|
|
.radr(radr[10:2]),
|
|
.o(tag)
|
|
);
|
|
|
|
|
|
always @(rclk)
|
|
rradr <= radr;
|
|
|
|
assign hit = tag[31:11]==rradr[31:11];
|
|
|
|
endmodule
|
|
|
|
module overflow(op, a, b, s, v);
|
|
|
|
input op; // 0=add,1=sub
|
|
input a;
|
|
input b;
|
|
input s; // sum
|
|
output v;
|
|
|
|
// Overflow:
|
|
// Add: the signs of the inputs are the same, and the sign of the
|
|
// sum is different
|
|
// Sub: the signs of the inputs are different, and the sign of
|
|
// the sum is the same as B
|
|
assign v = (op ^ s ^ b) & (~op ^ a ^ b);
|
|
|
|
endmodule
|
|
/*
|
|
// This table being setup to set the pc increment. It should synthesize to a ROM.
|
|
module m_pcinc(opcode,inc);
|
|
input [7:0] opcode;
|
|
output [3:0] inc;
|
|
|
|
always @(opcode)
|
|
if (em)
|
|
else
|
|
case(opcode)
|
|
`BRK: inc <= 4'd1;
|
|
`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA: inc <= 4'd2;
|
|
`BRL: inc <= 4'd3;
|
|
`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
|
|
`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
|
|
`TRS,`TSR: inc <= 4'd2;
|
|
`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
|
|
`EMM: inc <= 4'd1;
|
|
`PHA,`PHX,`PHY,`PHP: inc <= 4'd1;
|
|
`PLA,`PLX,`PLY,`PLP: inc <= 4'd1;
|
|
`PUSH,`POP: inc <= 4'd2;
|
|
`STP,`WAI: inc <= 4'd1;
|
|
`JMP,`JSR: inc <= 4'd3;
|
|
`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
|
|
`JMP_RIND,`JSR_RIND: inc <= 4'd2;
|
|
`RTS,`RTI,`RTL: inc <= 4'd1;
|
|
`NOP: inc <= 4'd1;
|
|
`BSR: inc <= 4'd3;
|
|
`RR: inc <= 4'd3;
|
|
`LD_RR: inc <= 4'd2;
|
|
`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8: inc <= 4'd2;
|
|
`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd3;
|
|
`ADD_IMM32,`SUB_IMM32,`AND_IMM32,`OR_IMM32,`EOR_IMM32: inc <= 4'd5;
|
|
`ADD_ZPX,`SUB_ZPX,`AND_ZPX,`OR_ZPX,`EOR_ZPX: inc <= 4'd4;
|
|
`ADD_IX,`SUB_IX,`AND_IX,`OR_IX,`EOR_IX: inc <= 4'd4;
|
|
`ADD_IY,`SUB_IY,`AND_IY,`OR_IY,`EOR_IY: inc <= 4'd4;
|
|
`ADD_ABS,`SUB_ABS,`AND_ABS,`OR_ABS,`EOR_ABS: inc <= 4'd6;
|
|
`ADD_ABSX,`SUB_ABSX,`AND_ABSX,`OR_ABSX,`EOR_ABSX: inc <= 4'd7;
|
|
`ADD_RIND,`SUB_RIND,`AND_RIND,`OR_RIND,`EOR_RIND: inc <= 4'd2;
|
|
`ADD_DSP,`SUB_DSP,`AND_DSP,`OR_DSP,`EOR_DSP: inc <= 4'd3;
|
|
endcase
|
|
endmodule*/
|
|
|
|
|
|
|
|
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
parameter IDLE = 3'd0;
|
parameter IDLE = 3'd0;
|
parameter LOAD_DCACHE = 3'd1;
|
parameter LOAD_DCACHE = 3'd1;
|
parameter LOAD_ICACHE = 3'd2;
|
parameter LOAD_ICACHE = 3'd2;
|
parameter LOAD_IBUF1 = 3'd3;
|
parameter LOAD_IBUF1 = 3'd3;
|
parameter LOAD_IBUF2 = 3'd4;
|
parameter LOAD_IBUF2 = 3'd4;
|
parameter LOAD_IBUF3 = 3'd5;
|
parameter LOAD_IBUF3 = 3'd5;
|
parameter RESET1 = 7'd0;
|
parameter RESET1 = 6'd0;
|
parameter IFETCH = 7'd1;
|
parameter IFETCH = 6'd1;
|
parameter JMP_IND1 = 7'd2;
|
parameter DECODE = 6'd2;
|
parameter JMP_IND2 = 7'd3;
|
parameter STORE1 = 6'd3;
|
parameter DECODE = 7'd4;
|
parameter STORE2 = 6'd4;
|
parameter STORE1 = 7'd5;
|
parameter IRQ0 = 6'd5;
|
parameter STORE2 = 7'd6;
|
parameter IRQ1 = 6'd6;
|
parameter LOAD1 = 7'd7;
|
parameter IRQ2 = 6'd7;
|
parameter LOAD2 = 7'd8;
|
parameter IRQ3 = 6'd8;
|
parameter IRQ1 = 7'd9;
|
parameter CALC = 6'd9;
|
parameter IRQ2 = 7'd10;
|
parameter JSR_INDX1 = 6'd10;
|
parameter IRQ3 = 7'd11;
|
parameter JSR161 = 6'd11;
|
parameter CALC = 7'd12;
|
parameter RTS1 = 6'd12;
|
parameter JSR1 = 7'd13;
|
parameter IY3 = 6'd13;
|
parameter JSR_INDX1 = 7'd14;
|
parameter BSR1 = 6'd14;
|
parameter JSR161 = 7'd15;
|
parameter BYTE_IX5 = 6'd15;
|
parameter RTS1 = 7'd16;
|
parameter BYTE_IY5 = 6'd16;
|
parameter IX1 = 7'd18;
|
parameter BYTE_JSR1 = 6'd17;
|
parameter IX2 = 7'd19;
|
parameter BYTE_JSR2 = 6'd18;
|
parameter IX3 = 7'd20;
|
parameter BYTE_JSR3 = 6'd19;
|
parameter IX4 = 7'd21;
|
parameter BYTE_IRQ1 = 6'd20;
|
parameter IY1 = 7'd22;
|
parameter BYTE_IRQ2 = 6'd21;
|
parameter IY2 = 7'd23;
|
parameter BYTE_IRQ3 = 6'd22;
|
parameter IY3 = 7'd24;
|
parameter BYTE_IRQ4 = 6'd23;
|
parameter BSR1 = 7'd32;
|
parameter BYTE_IRQ5 = 6'd24;
|
parameter BYTE_IX5 = 7'd37;
|
parameter BYTE_IRQ6 = 6'd25;
|
parameter BYTE_IY5 = 7'd42;
|
parameter BYTE_IRQ7 = 6'd26;
|
parameter BYTE_JSR1 = 7'd46;
|
parameter BYTE_IRQ8 = 6'd27;
|
parameter BYTE_JSR2 = 7'd47;
|
parameter BYTE_IRQ9 = 6'd28;
|
parameter BYTE_JSR3 = 7'd48;
|
parameter BYTE_JSR_INDX1 = 6'd29;
|
parameter BYTE_IRQ1 = 7'd49;
|
parameter BYTE_JSR_INDX2 = 6'd30;
|
parameter BYTE_IRQ2 = 7'd50;
|
parameter BYTE_JSR_INDX3 = 6'd31;
|
parameter BYTE_IRQ3 = 7'd51;
|
parameter BYTE_JSL1 = 6'd32;
|
parameter BYTE_IRQ4 = 7'd52;
|
parameter BYTE_JSL2 = 6'd33;
|
parameter BYTE_IRQ5 = 7'd53;
|
parameter BYTE_JSL3 = 6'd34;
|
parameter BYTE_IRQ6 = 7'd54;
|
parameter BYTE_JSL4 = 6'd35;
|
parameter BYTE_IRQ7 = 7'd55;
|
parameter BYTE_JSL5 = 6'd36;
|
parameter BYTE_IRQ8 = 7'd56;
|
parameter BYTE_JSL6 = 6'd37;
|
parameter BYTE_IRQ9 = 7'd57;
|
parameter BYTE_JSL7 = 6'd38;
|
parameter BYTE_JMP_IND1 = 7'd58;
|
parameter BYTE_PLP1 = 6'd39;
|
parameter BYTE_JMP_IND2 = 7'd59;
|
parameter BYTE_PLP2 = 6'd40;
|
parameter BYTE_JMP_IND3 = 7'd60;
|
parameter BYTE_PLA1 = 6'd41;
|
parameter BYTE_JMP_IND4 = 7'd61;
|
parameter BYTE_PLA2 = 6'd42;
|
parameter BYTE_JSR_INDX1 = 7'd62;
|
parameter WAIT_DHIT = 6'd43;
|
parameter BYTE_JSR_INDX2 = 7'd63;
|
parameter RESET2 = 6'd44;
|
parameter BYTE_JSR_INDX3 = 7'd64;
|
parameter MULDIV1 = 6'd45;
|
parameter RTI1 = 7'd65;
|
parameter MULDIV2 = 6'd46;
|
parameter RTI2 = 7'd66;
|
parameter BYTE_DECODE = 6'd47;
|
parameter RTI3 = 7'd67;
|
parameter BYTE_CALC = 6'd48;
|
parameter RTI4 = 7'd68;
|
parameter BUS_ERROR = 6'd49;
|
parameter BYTE_RTS1 = 7'd69;
|
parameter INSN_BUS_ERROR = 6'd50;
|
parameter BYTE_RTS2 = 7'd70;
|
parameter LOAD_MAC1 = 6'd51;
|
parameter BYTE_RTS3 = 7'd71;
|
parameter LOAD_MAC2 = 6'd52;
|
parameter BYTE_RTS4 = 7'd72;
|
parameter MVN1 = 6'd53;
|
parameter BYTE_RTS5 = 7'd73;
|
parameter MVN2 = 6'd54;
|
parameter BYTE_RTS6 = 7'd74;
|
parameter MVN3 = 6'd55;
|
parameter BYTE_RTS7 = 7'd75;
|
parameter MVP1 = 6'd56;
|
parameter BYTE_RTS8 = 7'd76;
|
parameter MVP2 = 6'd57;
|
parameter BYTE_RTS9 = 7'd77;
|
parameter STS1 = 6'd58;
|
parameter BYTE_RTI1 = 7'd78;
|
|
parameter BYTE_RTI2 = 7'd79;
|
|
parameter BYTE_RTI3 = 7'd80;
|
|
parameter BYTE_RTI4 = 7'd81;
|
|
parameter BYTE_RTI5 = 7'd82;
|
|
parameter BYTE_RTI6 = 7'd83;
|
|
parameter BYTE_RTI7 = 7'd84;
|
|
parameter BYTE_RTI8 = 7'd85;
|
|
parameter BYTE_RTI9 = 7'd86;
|
|
parameter BYTE_RTI10 = 7'd87;
|
|
parameter BYTE_JSL1 = 7'd88;
|
|
parameter BYTE_JSL2 = 7'd89;
|
|
parameter BYTE_JSL3 = 7'd90;
|
|
parameter BYTE_JSL4 = 7'd91;
|
|
parameter BYTE_JSL5 = 7'd92;
|
|
parameter BYTE_JSL6 = 7'd93;
|
|
parameter BYTE_JSL7 = 7'd94;
|
|
parameter BYTE_PLP1 = 7'd95;
|
|
parameter BYTE_PLP2 = 7'd96;
|
|
parameter BYTE_PLA1 = 7'd97;
|
|
parameter BYTE_PLA2 = 7'd98;
|
|
parameter WAIT_DHIT = 7'd99;
|
|
parameter RESET2 = 7'd100;
|
|
parameter MULDIV1 = 7'd101;
|
|
parameter MULDIV2 = 7'd102;
|
|
parameter BYTE_DECODE = 7'd103;
|
|
parameter BYTE_CALC = 7'd104;
|
|
parameter BUS_ERROR = 7'd105;
|
|
parameter INSN_BUS_ERROR = 7'd106;
|
|
parameter LOAD_MAC1 = 7'd107;
|
|
parameter LOAD_MAC2 = 7'd108;
|
|
parameter MVN1 = 7'd109;
|
|
parameter MVN2 = 7'd110;
|
|
parameter MVN3 = 7'd111;
|
|
parameter MVP1 = 7'd112;
|
|
parameter MVP2 = 7'd113;
|
|
|
|
input rst_md; // reset mode, 1=emulation mode, 0=native mode
|
input rst_md; // reset mode, 1=emulation mode, 0=native mode
|
input rst_i;
|
input rst_i;
|
input clk_i;
|
input clk_i;
|
input nmi_i;
|
input nmi_i;
|
| Line 810... |
Line 111... |
output reg [3:0] sel_o;
|
output reg [3:0] sel_o;
|
output reg [33:0] adr_o;
|
output reg [33:0] adr_o;
|
input [31:0] dat_i;
|
input [31:0] dat_i;
|
output reg [31:0] dat_o;
|
output reg [31:0] dat_o;
|
|
|
reg [6:0] state;
|
reg [5:0] state;
|
reg [6:0] retstate;
|
reg [5:0] retstate;
|
reg [2:0] cstate;
|
reg [2:0] cstate;
|
wire [63:0] insn;
|
wire [63:0] insn;
|
reg [63:0] ibuf;
|
reg [63:0] ibuf;
|
reg [31:0] bufadr;
|
reg [31:0] bufadr;
|
reg [63:0] exbuf;
|
reg [63:0] exbuf;
|
| Line 846... |
Line 147... |
wire [31:0] isp_dec = isp - 32'd1;
|
wire [31:0] isp_dec = isp - 32'd1;
|
wire [31:0] isp_inc = isp + 32'd1;
|
wire [31:0] isp_inc = isp + 32'd1;
|
reg [3:0] suppress_pcinc;
|
reg [3:0] suppress_pcinc;
|
reg [31:0] pc;
|
reg [31:0] pc;
|
reg [31:0] opc;
|
reg [31:0] opc;
|
wire [31:0] pcp1 = pc + (32'd1 & suppress_pcinc);
|
wire [3:0] pc_inc;
|
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc);
|
wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
|
wire [31:0] pcp3 = pc + (32'd3 & suppress_pcinc);
|
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
|
wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc);
|
wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
|
wire [31:0] pcp5 = pc + (32'd5 & suppress_pcinc);
|
|
wire [31:0] pcp6 = pc + (32'd6 & suppress_pcinc);
|
|
wire [31:0] pcp7 = pc + (32'd7 & suppress_pcinc);
|
|
wire [31:0] pcp8 = pc + (32'd8 & suppress_pcinc);
|
|
reg [31:0] dp; // 32 bit mode direct page register
|
|
reg [31:0] dp8; // 8 bit mode direct page register
|
|
reg [31:0] abs8; // 8 bit mode absolute address register
|
reg [31:0] abs8; // 8 bit mode absolute address register
|
reg [31:0] vbr; // vector table base register
|
reg [31:0] vbr; // vector table base register
|
wire bhit=pc==bufadr;
|
wire bhit=pc==bufadr;
|
reg [31:0] regfile [15:0];
|
reg [31:0] regfile [15:0];
|
reg [63:0] ir;
|
reg [63:0] ir;
|
| Line 888... |
Line 183... |
reg first_ifetch;
|
reg first_ifetch;
|
reg [31:0] lfsr;
|
reg [31:0] lfsr;
|
wire lfsr_fb;
|
wire lfsr_fb;
|
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
|
xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
|
reg [31:0] a, b;
|
reg [31:0] a, b;
|
|
`ifdef SUPPORT_SHIFT
|
wire [31:0] shlo = a << b[4:0];
|
wire [31:0] shlo = a << b[4:0];
|
wire [31:0] shro = a >> b[4:0];
|
wire [31:0] shro = a >> b[4:0];
|
|
`else
|
|
wire [31:0] shlo = 32'd0;
|
|
wire [31:0] shro = 32'd0;
|
|
`endif
|
reg [7:0] b8;
|
reg [7:0] b8;
|
reg [32:0] res;
|
reg [32:0] res;
|
reg [8:0] res8;
|
reg [8:0] res8;
|
wire resv8,resv32;
|
wire resv8,resv32;
|
wire resc8 = res8[8];
|
wire resc8 = res8[8];
|
wire resc32 = res[32];
|
wire resc32 = res[32];
|
wire resz8 = res8[7:0]==8'h00;
|
wire resz8 = res8[7:0]==8'h00;
|
wire resz32 = res[31:0]==32'd0;
|
wire resz32 = res[31:0]==32'd0;
|
wire resn8 = res8[7];
|
wire resn8 = res8[7];
|
wire resn32 = res[31];
|
wire resn32 = res[31];
|
wire resn = em ? res8[7] : res[31];
|
|
wire resz = em ? res8[7:0]==8'h00 : res[31:0]==32'd0;
|
|
wire resc = em ? res8[8] : res[32];
|
|
wire resv = em ? resv8 : resv32;
|
|
|
|
reg [31:0] vect;
|
reg [31:0] vect;
|
reg [31:0] ia; // temporary reg to hold indirect address
|
reg [31:0] ia; // temporary reg to hold indirect address
|
wire [31:0] iapy8 = abs8 + ia + y[7:0];
|
wire [31:0] iapy8 = abs8 + ia + y[7:0];
|
reg isInsnCacheLoad;
|
reg isInsnCacheLoad;
|
reg isDataCacheLoad;
|
reg isDataCacheLoad;
|
reg isCacheReset;
|
reg isCacheReset;
|
wire hit0,hit1;
|
wire hit0,hit1;
|
|
`ifdef SUPPORT_DCACHE
|
wire dhit;
|
wire dhit;
|
|
`else
|
|
wire dhit = 1'b0;
|
|
`endif
|
reg write_allocate;
|
reg write_allocate;
|
reg wr;
|
reg wr;
|
reg [3:0] wrsel;
|
reg [3:0] wrsel;
|
reg [31:0] radr;
|
reg [31:0] radr;
|
reg [1:0] radr2LSB;
|
reg [1:0] radr2LSB;
|
| Line 930... |
Line 230... |
reg [3:0] store_what;
|
reg [3:0] store_what;
|
reg [31:0] derr_address;
|
reg [31:0] derr_address;
|
reg imiss;
|
reg imiss;
|
reg dmiss;
|
reg dmiss;
|
reg icacheOn,dcacheOn;
|
reg icacheOn,dcacheOn;
|
|
`ifdef SUPPORT_DCACHE
|
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
|
wire unCachedData = radr[31:20]==12'hFFD || !dcacheOn; // I/O area is uncached
|
|
`else
|
|
wire unCachedData = 1'b1;
|
|
`endif
|
|
`ifdef SUPPORT_ICACHE
|
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
|
wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
|
|
`else
|
|
wire unCachedInsn = 1'b1;
|
|
`endif
|
|
|
|
reg [31:0] history_buf [63:0];
|
|
reg [5:0] history_ndx;
|
|
reg hist_capture;
|
|
|
|
reg isBrk,isMove,isSts;
|
|
reg isRTI,isRTL,isRTS;
|
|
reg isOrb,isStb;
|
|
reg isRMW;
|
|
reg isSub,isSub8;
|
|
|
|
|
wire isSub = ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
|
|
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
|
|
wire isSub8 = ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
|
|
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
|
|
wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
|
wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
|
ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
|
ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
|
wire isRMW32 =
|
wire isRMW32 =
|
ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
|
ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
|
ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
|
ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
|
| Line 952... |
Line 267... |
ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
|
ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
|
ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
|
ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
|
ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
|
ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
|
ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
|
ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
|
;
|
;
|
wire isRMW = em ? isRMW8 : isRMW32;
|
|
wire isOrb = ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
|
// Registerable decodes
|
wire isStb = ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
|
// The following decodes can be registered because they aren't needed until at least the cycle after
|
wire isRTI = ir[7:0]==`RTI;
|
// the DECODE stage.
|
wire isRTL = ir[7:0]==`RTL;
|
|
wire isRTS = ir[7:0]==`RTS;
|
always @(posedge clk)
|
wire isMove = ir[7:0]==`MVP || ir[7:0]==`MVN;
|
if (state==DECODE) begin
|
|
isSub <= ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
|
|
ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
|
|
isSub8 <= ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
|
|
ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
|
|
isRMW <= em ? isRMW8 : isRMW32;
|
|
isOrb <= ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
|
|
isStb <= ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
|
|
isRTI <= ir[7:0]==`RTI;
|
|
isRTL <= ir[7:0]==`RTL;
|
|
isRTS <= ir[7:0]==`RTS;
|
|
isBrk <= ir[7:0]==`BRK;
|
|
isMove <= ir[7:0]==`MVP || ir[7:0]==`MVN;
|
|
isSts <= ir[7:0]==`STS;
|
|
end
|
|
|
|
`ifdef SUPPORT_EXEC
|
wire isExec = ir[7:0]==`EXEC;
|
wire isExec = ir[7:0]==`EXEC;
|
wire isAtni = ir[7:0]==`ATNI;
|
wire isAtni = ir[7:0]==`ATNI;
|
|
`else
|
|
wire isExec = 1'b0;
|
|
wire isAtni = 1'b0;
|
|
`endif
|
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
|
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
|
wire md_done;
|
wire md_done;
|
wire clk;
|
wire clk;
|
reg isIY;
|
reg isIY;
|
|
|
|
rtf65002_pcinc upci1
|
|
(
|
|
.opcode(ir[7:0]),
|
|
.suppress_pcinc(suppress_pcinc),
|
|
.inc(pc_inc)
|
|
);
|
|
|
mult_div umd1
|
mult_div umd1
|
(
|
(
|
.rst(rst),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.ld(ld_muldiv),
|
.ld(ld_muldiv),
|
.op(ir[23:20]),
|
.op(ir[23:20]),
|
.a(rfoa),
|
.a(rfoa),
|
.b(rfob),
|
.b(rfob),
|
| Line 980... |
Line 322... |
.q(q),
|
.q(q),
|
.r(r),
|
.r(r),
|
.done(md_done)
|
.done(md_done)
|
);
|
);
|
|
|
icachemem icm0 (
|
`ifdef SUPPORT_ICACHE
|
|
rtf65002_icachemem icm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(ack_i & isInsnCacheLoad),
|
.wr(ack_i & isInsnCacheLoad),
|
.adr(adr_o),
|
.adr(adr_o),
|
.dat(dat_i),
|
.dat(dat_i),
|
.rclk(~clk_i),
|
.rclk(~clk),
|
.pc(pc),
|
.pc(pc),
|
.insn(insn)
|
.insn(insn)
|
);
|
);
|
|
|
tagmem tgm0 (
|
rtf65002_itagmem tgm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
|
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
|
.adr({adr_o[31:1],!isCacheReset}),
|
.adr({adr_o[31:1],!isCacheReset}),
|
.rclk(~clk_i),
|
.rclk(~clk),
|
.pc(pc),
|
.pc(pc),
|
.hit0(hit0),
|
.hit0(hit0),
|
.hit1(hit1)
|
.hit1(hit1)
|
);
|
);
|
|
|
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
|
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
|
|
`else
|
|
wire ihit = 1'b0;
|
|
`endif
|
|
|
dcachemem dcm0 (
|
`ifdef SUPPORT_DCACHE
|
|
rtf65002_dcachemem dcm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.sel(wr ? wrsel : sel_o),
|
.sel(wr ? wrsel : sel_o),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.wdat(wr ? wdat : dat_i),
|
.wdat(wr ? wdat : dat_i),
|
.rclk(~clk_i),
|
.rclk(~clk),
|
.radr(radr),
|
.radr(radr),
|
.rdat(rdat)
|
.rdat(rdat)
|
);
|
);
|
|
|
dtagmem dtm0 (
|
rtf65002_dtagmem dtm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.rclk(~clk_i),
|
.rclk(~clk),
|
.radr(radr),
|
.radr(radr),
|
.hit(dhit)
|
.hit(dhit)
|
);
|
);
|
|
`endif
|
|
|
overflow uovr1 (
|
overflow uovr1 (
|
.op(isSub),
|
.op(isSub),
|
.a(a[31]),
|
.a(a[31]),
|
.b(b[31]),
|
.b(b[31]),
|
| Line 1044... |
Line 392... |
wire [7:0] bcao;
|
wire [7:0] bcao;
|
wire [7:0] bcsio;
|
wire [7:0] bcsio;
|
wire [7:0] bcso;
|
wire [7:0] bcso;
|
wire bcaico,bcaco,bcsico,bcsco;
|
wire bcaico,bcaco,bcsico,bcsco;
|
|
|
|
`ifdef SUPPORT_BCD
|
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
|
BCDAdd ubcdai1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcaio),.c(bcaico));
|
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
|
BCDAdd ubcda2 (.ci(cf),.a(acc8),.b(b8),.o(bcao),.c(bcaco));
|
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
|
BCDSub ubcdsi1 (.ci(cf),.a(acc8),.b(ir[15:8]),.o(bcsio),.c(bcsico));
|
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
|
BCDSub ubcds2 (.ci(cf),.a(acc8),.b(b8),.o(bcso),.c(bcsco));
|
|
`endif
|
|
|
reg [7:0] dati;
|
reg [7:0] dati;
|
always @(radr2LSB or dat_i)
|
always @(radr2LSB or dat_i)
|
case(radr2LSB)
|
case(radr2LSB)
|
2'd0: dati <= dat_i[7:0];
|
2'd0: dati <= dat_i[7:0];
|
| Line 1079... |
Line 429... |
`BCC: takb <= !cf;
|
`BCC: takb <= !cf;
|
`BVS: takb <= vf;
|
`BVS: takb <= vf;
|
`BVC: takb <= !vf;
|
`BVC: takb <= !vf;
|
`BRA: takb <= 1'b1;
|
`BRA: takb <= 1'b1;
|
`BRL: takb <= 1'b1;
|
`BRL: takb <= 1'b1;
|
|
`BHI: takb <= cf & !zf;
|
|
`BLS: takb <= !cf | zf;
|
|
`BGE: takb <= (nf & vf)|(!nf & !vf);
|
|
`BLT: takb <= (nf & !vf)|(!nf & vf);
|
|
`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
|
|
`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
|
//`BAZ: takb <= acc8==8'h00;
|
//`BAZ: takb <= acc8==8'h00;
|
//`BXZ: takb <= x8==8'h00;
|
//`BXZ: takb <= x8==8'h00;
|
default: takb <= 1'b0;
|
default: takb <= 1'b0;
|
endcase
|
endcase
|
|
|
wire [31:0] zp_address = dp8 + ir[15:8];
|
wire [31:0] zp_address = {abs8[31:12],4'h0,ir[15:8]};
|
wire [31:0] zpx_address = zp_address + x8;
|
wire [31:0] zpx_address = {abs8[31:12],4'h0,ir[15:8]} + x8;
|
wire [31:0] zpy_address = zp_address + y8;
|
wire [31:0] zpy_address = {abs8[31:12],4'h0,ir[15:8]} + y8;
|
wire [31:0] abs_address = abs8 + {16'h0,ir[23:8]};
|
wire [31:0] abs_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8]};
|
wire [31:0] absx_address = abs8 + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
|
wire [31:0] absx_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
|
wire [31:0] absy_address = abs8 + {16'h0,ir[23:8] + {8'h0,y8}};
|
wire [31:0] absy_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,y8}};
|
wire [31:0] zpx32xy_address = dp + ir[23:12] + rfoa;
|
wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
|
wire [31:0] absx32xy_address = ir[47:16] + rfob;
|
wire [31:0] absx32xy_address = ir[47:16] + rfob;
|
wire [31:0] zpx32_address = dp + ir[31:20] + rfob;
|
wire [31:0] zpx32_address = ir[31:20] + rfob;
|
wire [31:0] absx32_address = ir[55:24] + rfob;
|
wire [31:0] absx32_address = ir[55:24] + rfob;
|
|
|
|
reg [32:0] calc_res;
|
|
always @(a or b or b8 or x or y or df or cf or Rt or shlo or shro)
|
|
begin
|
|
case(ir[7:0])
|
|
`RR:
|
|
case(ir[23:20])
|
|
`ASL_RRR: calc_res <= shlo;
|
|
`LSR_RRR: calc_res <= shro;
|
|
default: calc_res <= 33'd0;
|
|
endcase
|
|
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: calc_res <= a + b + {31'b0,df&cf};
|
|
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: calc_res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
|
|
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: calc_res <= a & b; // Also BIT
|
|
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: calc_res <= a | b; // Also LD
|
|
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: calc_res <= a ^ b;
|
|
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: calc_res <= b;
|
|
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: calc_res <= b;
|
|
`CPX_ZPX,`CPX_ABS: calc_res <= x - b;
|
|
`CPY_ZPX,`CPY_ABS: calc_res <= y - b;
|
|
`ASL_IMM8: calc_res <= shlo;
|
|
`LSR_IMM8: calc_res <= shro;
|
|
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: calc_res <= {b,1'b0};
|
|
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: calc_res <= {b,cf};
|
|
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: calc_res <= {b[0],1'b0,b[31:1]};
|
|
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: calc_res <= {b[0],cf,b[31:1]};
|
|
`INC_ZPX,`INC_ABS,`INC_ABSX: calc_res <= b + 32'd1;
|
|
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: calc_res <= b - 32'd1;
|
|
`ORB_ZPX,`ORB_ABS,`ORB_ABSX: calc_res <= a | {24'h0,b8};
|
|
default: calc_res <= 33'd0;
|
|
endcase
|
|
end
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Clock control
|
// Clock control
|
// - reset or NMI reenables the clock
|
// - reset or NMI reenables the clock
|
// - this circuit must be under the clk_i domain
|
// - this circuit must be under the clk_i domain
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
| Line 1134... |
Line 523... |
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
wai <= 1'b0;
|
wai <= 1'b0;
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
wr <= 1'b0;
|
wr <= 1'b0;
|
cf <= 1'b0;
|
cf <= 1'b0;
|
ir <= 56'hEAEAEAEAEAEAEA;
|
ir <= 64'hEAEAEAEAEAEAEAEA;
|
imiss <= `FALSE;
|
imiss <= `FALSE;
|
dmiss <= `FALSE;
|
dmiss <= `FALSE;
|
dcacheOn <= 1'b0;
|
dcacheOn <= 1'b0;
|
icacheOn <= 1'b1;
|
icacheOn <= 1'b1;
|
write_allocate <= 1'b0;
|
write_allocate <= 1'b0;
|
| Line 1157... |
Line 546... |
end
|
end
|
suppress_pcinc <= 4'hF;
|
suppress_pcinc <= 4'hF;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
spage <= 32'h00000100;
|
spage <= 32'h00000100;
|
bufadr <= 32'd0;
|
bufadr <= 32'd0;
|
dp <= 32'd0;
|
|
dp8 <= 32'd0;
|
|
abs8 <= 32'd0;
|
abs8 <= 32'd0;
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
isCacheReset <= `TRUE;
|
isCacheReset <= `TRUE;
|
gie <= 1'b0;
|
gie <= 1'b0;
|
tick <= 32'd0;
|
tick <= 32'd0;
|
isIY <= 1'b0;
|
isIY <= 1'b0;
|
|
load_what <= `NOTHING;
|
|
hist_capture <= `TRUE;
|
|
history_ndx <= 6'd0;
|
end
|
end
|
else begin
|
else begin
|
tick <= tick + 32'd1;
|
tick <= tick + 32'd1;
|
wr <= 1'b0;
|
wr <= 1'b0;
|
if (nmi_i & !nmi1)
|
if (nmi_i & !nmi1)
|
| Line 1192... |
Line 582... |
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
|
`include "ifetch.v"
|
`include "ifetch.v"
|
`include "decode.v"
|
`include "decode.v"
|
|
`ifdef SUPPORT_EM8
|
`include "byte_decode.v"
|
`include "byte_decode.v"
|
|
`include "byte_calc.v"
|
|
`include "byte_jsr.v"
|
|
`include "byte_jsl.v"
|
|
`ifdef SUPPORT_BYTE_IRQ
|
|
`include "byte_irq.v"
|
|
`endif
|
|
`endif
|
|
|
`include "load_mac.v"
|
`include "load_mac.v"
|
`include "store.v"
|
`include "store.v"
|
|
|
WAIT_DHIT:
|
WAIT_DHIT:
|
if (dhit)
|
if (dhit)
|
state <= retstate;
|
state <= retstate;
|
|
|
`include "byte_calc.v"
|
|
`include "calc.v"
|
`include "calc.v"
|
`include "byte_jsr.v"
|
|
`include "byte_jsl.v"
|
|
|
|
JSR1:
|
|
if (ack_i) begin
|
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
pc <= vect;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
|
|
JSR_INDX1:
|
JSR_INDX1:
|
if (ack_i) begin
|
if (ack_i) begin
|
load_what <= `PC_310;
|
load_what <= `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
| Line 1270... |
Line 643... |
else if (write_allocate) begin
|
else if (write_allocate) begin
|
state <= WAIT_DHIT;
|
state <= WAIT_DHIT;
|
dmiss <= `TRUE;
|
dmiss <= `TRUE;
|
end
|
end
|
end
|
end
|
|
/*
|
`include "byte_irq.v"
|
IRQ0:
|
|
begin
|
IRQ1:
|
cyc_o <= 1'b1;
|
if (ack_i) begin
|
stb_o <= 1'b1;
|
ir <= 64'd0; // Force instruction decoder to BRK
|
we_o <= 1'b1;
|
state <= IRQ2;
|
sel_o <= 4'hF;
|
retstate <= IRQ2;
|
adr_o <= {wadr,2'b00};
|
cyc_o <= 1'b0;
|
dat_o <= wdat;
|
stb_o <= 1'b0;
|
state <= IRQ1;
|
we_o <= 1'b0;
|
end
|
sel_o <= 4'h0;
|
IRQ1:
|
isp <= isp_dec;
|
if (ack_i) begin
|
if (dhit) begin
|
ir <= 64'd0; // Force instruction decoder to BRK
|
wrsel <= sel_o;
|
state <= IRQ2;
|
wr <= 1'b1;
|
retstate <= IRQ2;
|
end
|
cyc_o <= 1'b0;
|
else if (write_allocate) begin
|
stb_o <= 1'b0;
|
state <= WAIT_DHIT;
|
we_o <= 1'b0;
|
dmiss <= `TRUE;
|
sel_o <= 4'h0;
|
end
|
isp <= isp_dec;
|
end
|
`ifdef SUPPORT_DCACHE
|
IRQ2:
|
if (dhit) begin
|
begin
|
wrsel <= sel_o;
|
cyc_o <= 1'b1;
|
wr <= 1'b1;
|
stb_o <= 1'b1;
|
end
|
we_o <= 1'b1;
|
else if (write_allocate) begin
|
sel_o <= 4'hF;
|
state <= WAIT_DHIT;
|
radr <= isp_dec;
|
dmiss <= `TRUE;
|
wadr <= isp_dec;
|
end
|
wdat <= sr;
|
`endif
|
adr_o <= {isp_dec,2'b00};
|
end
|
dat_o <= sr;
|
IRQ2:
|
state <= IRQ3;
|
begin
|
end
|
cyc_o <= 1'b1;
|
IRQ3:
|
stb_o <= 1'b1;
|
if (ack_i) begin
|
we_o <= 1'b1;
|
load_what <= `PC_310;
|
sel_o <= 4'hF;
|
state <= LOAD_MAC1;
|
radr <= isp_dec;
|
retstate <= LOAD_MAC1;
|
wadr <= isp_dec;
|
cyc_o <= 1'b0;
|
wdat <= sr;
|
stb_o <= 1'b0;
|
adr_o <= {isp_dec,2'b00};
|
we_o <= 1'b0;
|
dat_o <= sr;
|
sel_o <= 4'h0;
|
state <= IRQ3;
|
isp <= isp_dec;
|
end
|
if (dhit) begin
|
IRQ3:
|
wrsel <= sel_o;
|
if (ack_i) begin
|
wr <= 1'b1;
|
load_what <= `PC_310;
|
end
|
state <= LOAD_MAC1;
|
else if (write_allocate) begin
|
retstate <= LOAD_MAC1;
|
dmiss <= `TRUE;
|
cyc_o <= 1'b0;
|
state <= WAIT_DHIT;
|
stb_o <= 1'b0;
|
end
|
we_o <= 1'b0;
|
radr <= vect[31:2];
|
sel_o <= 4'h0;
|
if (hwi)
|
isp <= isp_dec;
|
im <= 1'b1;
|
`ifdef SUPPORT_DCACHE
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
if (dhit) begin
|
end
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
|
`endif
|
|
radr <= vect[31:2];
|
|
if (hwi)
|
|
im <= 1'b1;
|
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
|
end
|
|
*/
|
MULDIV1:
|
MULDIV1:
|
state <= MULDIV2;
|
|
MULDIV2:
|
|
if (md_done) begin
|
if (md_done) begin
|
state <= IFETCH;
|
state <= IFETCH;
|
case(ir[23:20])
|
case(ir[23:20])
|
`MUL_RR: begin res <= prod[31:0]; end
|
`MUL_RR: begin res <= prod[31:0]; end
|
`MULS_RR: begin res <= prod[31:0]; end
|
`MULS_RR: begin res <= prod[31:0]; end
|
| Line 1344... |
Line 727... |
`MOD_RR: begin res <= r; end
|
`MOD_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
`ifdef SUPPORT_BERR
|
BUS_ERROR:
|
BUS_ERROR:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
wdat <= opc;
|
wdat <= opc;
|
if (em | isOrb | isStb)
|
if (em | isOrb | isStb)
|
derr_address <= adr_o[31:0];
|
derr_address <= adr_o[31:0];
|
else
|
else
|
derr_address <= adr_o[33:2];
|
derr_address <= adr_o[33:2];
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= opc;
|
|
vect <= {vbr[31:9],9'd508,2'b00};
|
vect <= {vbr[31:9],9'd508,2'b00};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
state <= IRQ1;
|
state <= IRQ0;
|
end
|
end
|
INSN_BUS_ERROR:
|
INSN_BUS_ERROR:
|
begin
|
begin
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
wdat <= opc;
|
wdat <= opc;
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= opc;
|
|
vect <= {vbr[31:9],9'd509,2'b00};
|
vect <= {vbr[31:9],9'd509,2'b00};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
state <= IRQ1;
|
state <= IRQ0;
|
end
|
end
|
/*
|
`endif
|
MVN1:
|
|
begin
|
`ifdef SUPPORT_STRING
|
radr <= x;
|
MVN1:
|
x <= x + 32'd1;
|
begin
|
retstate <= MVN2;
|
radr <= x;
|
load_what <= `WORD_312;
|
res <= x + 32'd1;
|
state <= LOAD_MAC1;
|
retstate <= MVN2;
|
end
|
load_what <= `WORD_312;
|
MVN2:
|
state <= LOAD_MAC1;
|
begin
|
end
|
radr <= y;
|
MVN2:
|
wadr <= y;
|
begin
|
wdat <= b;
|
radr <= y;
|
y <= y + 32'd1;
|
wadr <= y;
|
acc <= acc - 32'd1;
|
store_what <= `STW_B;
|
state <= STORE1;
|
x <= res;
|
end
|
res <= y + 32'd1;
|
MVN3:
|
acc <= acc - 32'd1;
|
begin
|
state <= STORE1;
|
state <= IFETCH;
|
end
|
if (acc==32'hFFFFFFFF)
|
MVN3:
|
pc <= pc + 32'd1;
|
begin
|
end
|
state <= IFETCH;
|
MVP1:
|
y <= res;
|
begin
|
if (acc==32'hFFFFFFFF)
|
radr <= x;
|
pc <= pc + 32'd1;
|
x <= x - 32'd1;
|
end
|
retstate <= MVP2;
|
MVP1:
|
load_what <= `WORD_312;
|
begin
|
state <= LOAD_MAC1;
|
radr <= x;
|
end
|
res <= x - 32'd1;
|
MVP2:
|
retstate <= MVP2;
|
begin
|
load_what <= `WORD_312;
|
radr <= y;
|
state <= LOAD_MAC1;
|
wadr <= y;
|
end
|
wdat <= b;
|
MVP2:
|
y <= y - 32'd1;
|
begin
|
acc <= acc - 32'd1;
|
radr <= y;
|
state <= STORE1;
|
wadr <= y;
|
end
|
store_what <= `STW_B;
|
*/
|
x <= res;
|
|
res <= y - 32'd1;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
|
end
|
|
STS1:
|
|
begin
|
|
radr <= y;
|
|
wadr <= y;
|
|
store_what <= `STW_X;
|
|
res <= y + 32'd1;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
|
end
|
|
`endif
|
|
|
endcase
|
endcase
|
|
|
`include "cache_controller.v"
|
`include "cache_controller.v"
|
|
|
end
|
end
|
