| Line 24... |
Line 24... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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`include "rtf65002_defines.v"
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`include "rtf65002_defines.v"
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module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
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module rtf65002d(rst_md, rst_i, clk_i, nmi_i, irq_i, irq_vect, bte_o, cti_o, bl_o, lock_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o, km_o);
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parameter IDLE = 3'd0;
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parameter LOAD_DCACHE = 3'd1;
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parameter LOAD_ICACHE = 3'd2;
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parameter LOAD_IBUF1 = 3'd3;
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parameter LOAD_IBUF2 = 3'd4;
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parameter LOAD_IBUF3 = 3'd5;
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parameter RESET1 = 6'd0;
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parameter RESET1 = 6'd0;
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parameter IFETCH = 6'd1;
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parameter IFETCH = 6'd1;
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parameter DECODE = 6'd2;
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parameter DECODE = 6'd2;
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parameter STORE1 = 6'd3;
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parameter STORE1 = 6'd3;
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parameter STORE2 = 6'd4;
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parameter STORE2 = 6'd4;
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parameter IRQ0 = 6'd5;
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parameter CALC = 6'd5;
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parameter IRQ1 = 6'd6;
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parameter JSR161 = 6'd6;
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parameter IRQ2 = 6'd7;
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parameter RTS1 = 6'd7;
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parameter IRQ3 = 6'd8;
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parameter IY3 = 6'd8;
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parameter CALC = 6'd9;
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parameter BSR1 = 6'd9;
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parameter JSR_INDX1 = 6'd10;
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parameter BYTE_IX5 = 6'd10;
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parameter JSR161 = 6'd11;
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parameter BYTE_IY5 = 6'd11;
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parameter RTS1 = 6'd12;
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parameter WAIT_DHIT = 6'd12;
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parameter IY3 = 6'd13;
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parameter RESET2 = 6'd13;
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parameter BSR1 = 6'd14;
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parameter MULDIV1 = 6'd14;
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parameter BYTE_IX5 = 6'd15;
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parameter MULDIV2 = 6'd15;
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parameter BYTE_IY5 = 6'd16;
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parameter BYTE_DECODE = 6'd16;
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parameter BYTE_JSR1 = 6'd17;
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parameter BYTE_CALC = 6'd17;
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parameter BYTE_JSR2 = 6'd18;
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parameter BUS_ERROR = 6'd18;
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parameter BYTE_JSR3 = 6'd19;
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parameter INSN_BUS_ERROR = 6'd19;
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parameter BYTE_IRQ1 = 6'd20;
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parameter LOAD_MAC1 = 6'd20;
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parameter BYTE_IRQ2 = 6'd21;
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parameter LOAD_MAC2 = 6'd21;
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parameter BYTE_IRQ3 = 6'd22;
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parameter LOAD_MAC3 = 6'd22;
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parameter BYTE_IRQ4 = 6'd23;
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parameter MVN3 = 6'd23;
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parameter BYTE_IRQ5 = 6'd24;
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parameter PUSHA1 = 6'd24;
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parameter BYTE_IRQ6 = 6'd25;
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parameter POPA1 = 6'd25;
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parameter BYTE_IRQ7 = 6'd26;
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parameter BYTE_IFETCH = 6'd26;
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parameter BYTE_IRQ8 = 6'd27;
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parameter LOAD_DCACHE = 6'd27;
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parameter BYTE_IRQ9 = 6'd28;
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parameter LOAD_ICACHE = 6'd28;
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parameter BYTE_JSR_INDX1 = 6'd29;
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parameter LOAD_IBUF1 = 6'd29;
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parameter BYTE_JSR_INDX2 = 6'd30;
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parameter LOAD_IBUF2 = 6'd30;
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parameter BYTE_JSR_INDX3 = 6'd31;
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parameter LOAD_IBUF3 = 6'd31;
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parameter BYTE_JSL1 = 6'd32;
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parameter ICACHE1 = 6'd32;
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parameter BYTE_JSL2 = 6'd33;
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parameter IBUF1 = 6'd33;
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parameter BYTE_JSL3 = 6'd34;
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parameter DCACHE1 = 6'd34;
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parameter BYTE_JSL4 = 6'd35;
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parameter CMPS1 = 6'd35;
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parameter BYTE_JSL5 = 6'd36;
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parameter BYTE_JSL6 = 6'd37;
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parameter BYTE_JSL7 = 6'd38;
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parameter BYTE_PLP1 = 6'd39;
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parameter BYTE_PLP2 = 6'd40;
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parameter BYTE_PLA1 = 6'd41;
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parameter BYTE_PLA2 = 6'd42;
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parameter WAIT_DHIT = 6'd43;
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parameter RESET2 = 6'd44;
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parameter MULDIV1 = 6'd45;
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parameter MULDIV2 = 6'd46;
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parameter BYTE_DECODE = 6'd47;
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parameter BYTE_CALC = 6'd48;
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parameter BUS_ERROR = 6'd49;
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parameter INSN_BUS_ERROR = 6'd50;
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parameter LOAD_MAC1 = 6'd51;
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parameter LOAD_MAC2 = 6'd52;
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parameter MVN1 = 6'd53;
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parameter MVN2 = 6'd54;
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parameter MVN3 = 6'd55;
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parameter MVP1 = 6'd56;
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parameter MVP2 = 6'd57;
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parameter STS1 = 6'd58;
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_md; // reset mode, 1=emulation mode, 0=native mode
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input rst_i;
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input rst_i;
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input clk_i;
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input clk_i;
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input nmi_i;
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input nmi_i;
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| Line 111... |
Line 82... |
output reg [3:0] sel_o;
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output reg [3:0] sel_o;
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output reg [33:0] adr_o;
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output reg [33:0] adr_o;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output reg [31:0] dat_o;
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output reg [31:0] dat_o;
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output km_o;
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reg [5:0] state;
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reg [5:0] state;
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reg [5:0] retstate;
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reg [5:0] retstate;
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reg [2:0] cstate;
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wire [63:0] insn;
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wire [63:0] insn;
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reg [63:0] ibuf;
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reg [63:0] ibuf;
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reg [31:0] bufadr;
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reg [31:0] bufadr;
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reg [63:0] exbuf;
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reg [63:0] exbuf;
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reg cf,nf,zf,vf,bf,im,df,em;
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reg cf,nf,zf,vf,bf,im,df,em;
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reg tf; // trace mode flag
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reg ttrig; // trace trigger
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reg em1;
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reg em1;
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reg gie;
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reg gie; // global interrupt enable (set when sp is loaded)
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reg hwi; // hardware interrupt indicator
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reg hwi; // hardware interrupt indicator
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reg nmoi; // native mode on interrupt
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reg nmoi; // native mode on interrupt
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wire [31:0] sr = {nf,vf,em,24'b0,bf,df,im,zf,cf};
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wire [31:0] sr = {nf,vf,em,tf,23'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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wire [7:0] sr8 = {nf,vf,1'b0,bf,df,im,zf,cf};
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reg nmi1,nmi_edge;
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reg nmi1,nmi_edge;
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reg wai;
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reg wai;
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reg [31:0] acc;
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reg [31:0] acc;
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reg [31:0] x;
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reg [31:0] x;
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| Line 147... |
Line 121... |
wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_dec = isp - 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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wire [31:0] isp_inc = isp + 32'd1;
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reg [3:0] suppress_pcinc;
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reg [3:0] suppress_pcinc;
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reg [31:0] pc;
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reg [31:0] pc;
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reg [31:0] opc;
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reg [31:0] opc;
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wire [3:0] pc_inc;
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wire [3:0] pc_inc,pc_inc8;
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wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
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wire [31:0] pcp2 = pc + (32'd2 & suppress_pcinc); // for branches
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wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
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wire [31:0] pcp4 = pc + (32'd4 & suppress_pcinc); // for branches
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wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
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wire [31:0] pcp8 = pc + 32'd8; // cache controller needs this
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reg [31:0] abs8; // 8 bit mode absolute address register
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reg [31:0] abs8; // 8 bit mode absolute address register
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reg [31:0] vbr; // vector table base register
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reg [31:0] vbr; // vector table base register
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wire bhit=pc==bufadr;
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wire bhit=pc==bufadr;
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reg [31:0] regfile [15:0];
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reg [31:0] regfile [15:0];
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reg [63:0] ir;
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reg [63:0] ir;
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reg pg2;
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wire [8:0] ir9 = {pg2,ir[7:0]};
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wire [3:0] Ra = ir[11:8];
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wire [3:0] Ra = ir[11:8];
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wire [3:0] Rb = ir[15:12];
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wire [3:0] Rb = ir[15:12];
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reg [31:0] rfoa;
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reg [31:0] rfoa;
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reg [31:0] rfob;
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reg [31:0] rfob;
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always @(Ra or x or y or acc)
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always @(Ra or x or y or acc)
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| Line 183... |
Line 159... |
reg first_ifetch;
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reg first_ifetch;
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reg [31:0] lfsr;
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reg [31:0] lfsr;
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wire lfsr_fb;
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wire lfsr_fb;
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xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
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xnor(lfsr_fb,lfsr[0],lfsr[1],lfsr[21],lfsr[31]);
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reg [31:0] a, b;
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reg [31:0] a, b;
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`ifdef SUPPORT_SHIFT
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wire signed [31:0] as = a;
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wire [31:0] shlo = a << b[4:0];
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wire signed [31:0] bs = b;
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wire [31:0] shro = a >> b[4:0];
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wire lt = as < bs;
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`else
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wire eq = a==b;
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wire [31:0] shlo = 32'd0;
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wire ltu = a < b;
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wire [31:0] shro = 32'd0;
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`endif
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reg [7:0] b8;
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reg [7:0] b8;
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wire [32:0] alu_out;
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reg [32:0] res;
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reg [32:0] res;
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reg [8:0] res8;
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reg [8:0] res8;
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wire resv8,resv32;
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wire resv8,resv32;
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wire resc8 = res8[8];
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wire resc8 = res8[8];
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wire resc32 = res[32];
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wire resc32 = res[32];
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| Line 203... |
Line 179... |
wire resn8 = res8[7];
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wire resn8 = res8[7];
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wire resn32 = res[31];
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wire resn32 = res[31];
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reg [31:0] vect;
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reg [31:0] vect;
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reg [31:0] ia; // temporary reg to hold indirect address
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reg [31:0] ia; // temporary reg to hold indirect address
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wire [31:0] iapy8 = abs8 + ia + y[7:0];
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reg isInsnCacheLoad;
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reg isInsnCacheLoad;
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reg isDataCacheLoad;
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reg isDataCacheLoad;
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reg isCacheReset;
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reg isCacheReset;
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wire hit0,hit1;
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wire hit0,hit1;
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`ifdef SUPPORT_DCACHE
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`ifdef SUPPORT_DCACHE
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wire dhit;
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wire dhit;
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`else
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`else
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wire dhit = 1'b0;
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wire dhit = 1'b0;
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`endif
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`endif
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reg write_allocate;
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reg write_allocate;
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reg wr;
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wire wr;
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reg [3:0] wrsel;
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reg [3:0] wrsel;
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reg [31:0] radr;
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reg [31:0] radr;
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reg [1:0] radr2LSB;
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reg [1:0] radr2LSB;
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wire [33:0] radr34 = {radr,radr2LSB};
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wire [33:0] radr34 = {radr,radr2LSB};
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wire [33:0] radr34p1 = radr34 + 34'd1;
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wire [33:0] radr34p1 = radr34 + 34'd1;
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reg [31:0] wadr;
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reg [31:0] wadr;
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reg [1:0] wadr2LSB;
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reg [1:0] wadr2LSB;
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reg [31:0] wdat;
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reg [31:0] wdat;
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wire [31:0] rdat;
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wire [31:0] rdat;
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reg [3:0] load_what;
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reg [4:0] load_what;
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reg [3:0] store_what;
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reg [5:0] store_what;
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reg [31:0] derr_address;
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reg [31:0] derr_address;
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reg imiss;
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reg imiss;
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reg dmiss;
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reg dmiss;
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reg icacheOn,dcacheOn;
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reg icacheOn,dcacheOn;
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`ifdef SUPPORT_DCACHE
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`ifdef SUPPORT_DCACHE
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| Line 240... |
Line 215... |
`ifdef SUPPORT_ICACHE
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`ifdef SUPPORT_ICACHE
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wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
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wire unCachedInsn = pc[31:13]==19'h0 || !icacheOn; // The lowest 8kB is uncached.
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`else
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`else
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wire unCachedInsn = 1'b1;
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wire unCachedInsn = 1'b1;
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`endif
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`endif
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`ifdef ICACHE_2WAY
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reg [31:0] clfsr;
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wire clfsr_fb;
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xnor(clfsr_fb,clfsr[0],clfsr[1],clfsr[21],clfsr[31]);
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wire [1:0] whichrd;
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wire whichwr=clfsr[0];
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`endif
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reg km; // kernel mode indicator
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assign km_o = km;
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reg [31:0] history_buf [63:0];
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reg [31:0] history_buf [127:0];
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reg [5:0] history_ndx;
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reg [6:0] history_ndx;
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reg hist_capture;
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reg hist_capture;
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reg isBusErr;
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reg isBrk,isMove,isSts;
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reg isBrk,isMove,isSts;
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reg isRTI,isRTL,isRTS;
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reg isRTI,isRTL,isRTS;
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reg isOrb,isStb;
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reg isOrb,isStb;
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reg isRMW;
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reg isRMW;
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reg isSub,isSub8;
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reg isSub,isSub8;
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reg isJsrIndx,isJsrInd;
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reg ldMuldiv;
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reg isPusha,isPopa;
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wire isCmp = ir9==`CPX_ZPX || ir9==`CPX_ABS || ir9==`CPX_IMM32 ||
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wire isCmp = ir[7:0]==`CPX_ZPX || ir[7:0]==`CPX_ABS || ir[7:0]==`CPX_IMM32 ||
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ir9==`CPY_ZPX || ir9==`CPY_ABS || ir9==`CPY_IMM32;
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ir[7:0]==`CPY_ZPX || ir[7:0]==`CPY_ABS || ir[7:0]==`CPY_IMM32;
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wire isRMW32 =
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wire isRMW32 =
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ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
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ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
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ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
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ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
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ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
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ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
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ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
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ir9==`TRB_ZP || ir9==`TRB_ZPX || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ZPX || ir9==`TSB_ABS ||
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ir9==`BMS_ZPX || ir9==`BMS_ABS || ir9==`BMS_ABSX ||
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ir9==`BMC_ZPX || ir9==`BMC_ABS || ir9==`BMC_ABSX ||
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ir9==`BMF_ZPX || ir9==`BMF_ABS || ir9==`BMF_ABSX
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;
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;
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wire isRMW8 =
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wire isRMW8 =
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ir[7:0]==`ASL_ZP || ir[7:0]==`ROL_ZP || ir[7:0]==`LSR_ZP || ir[7:0]==`ROR_ZP || ir[7:0]==`INC_ZP || ir[7:0]==`DEC_ZP ||
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ir9==`ASL_ZP || ir9==`ROL_ZP || ir9==`LSR_ZP || ir9==`ROR_ZP || ir9==`INC_ZP || ir9==`DEC_ZP ||
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ir[7:0]==`ASL_ZPX || ir[7:0]==`ROL_ZPX || ir[7:0]==`LSR_ZPX || ir[7:0]==`ROR_ZPX || ir[7:0]==`INC_ZPX || ir[7:0]==`DEC_ZPX ||
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ir9==`ASL_ZPX || ir9==`ROL_ZPX || ir9==`LSR_ZPX || ir9==`ROR_ZPX || ir9==`INC_ZPX || ir9==`DEC_ZPX ||
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ir[7:0]==`ASL_ABS || ir[7:0]==`ROL_ABS || ir[7:0]==`LSR_ABS || ir[7:0]==`ROR_ABS || ir[7:0]==`INC_ABS || ir[7:0]==`DEC_ABS ||
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ir9==`ASL_ABS || ir9==`ROL_ABS || ir9==`LSR_ABS || ir9==`ROR_ABS || ir9==`INC_ABS || ir9==`DEC_ABS ||
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ir[7:0]==`ASL_ABSX || ir[7:0]==`ROL_ABSX || ir[7:0]==`LSR_ABSX || ir[7:0]==`ROR_ABSX || ir[7:0]==`INC_ABSX || ir[7:0]==`DEC_ABSX ||
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ir9==`ASL_ABSX || ir9==`ROL_ABSX || ir9==`LSR_ABSX || ir9==`ROR_ABSX || ir9==`INC_ABSX || ir9==`DEC_ABSX ||
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ir[7:0]==`TRB_ZP || ir[7:0]==`TRB_ZPX || ir[7:0]==`TRB_ABS || ir[7:0]==`TSB_ZP || ir[7:0]==`TSB_ZPX || ir[7:0]==`TSB_ABS;
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ir9==`TRB_ZP || ir9==`TRB_ZPX || ir9==`TRB_ABS || ir9==`TSB_ZP || ir9==`TSB_ZPX || ir9==`TSB_ABS;
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;
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;
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// Registerable decodes
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// Registerable decodes
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// The following decodes can be registered because they aren't needed until at least the cycle after
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// The following decodes can be registered because they aren't needed until at least the cycle after
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// the DECODE stage.
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// the DECODE stage.
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always @(posedge clk)
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always @(posedge clk)
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if (state==DECODE) begin
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if (state==DECODE||state==BYTE_DECODE) begin
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isSub <= ir[7:0]==`SUB_ZPX || ir[7:0]==`SUB_IX || ir[7:0]==`SUB_IY ||
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isSub <= ir9==`SUB_ZPX || ir9==`SUB_IX || ir9==`SUB_IY ||
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ir[7:0]==`SUB_ABS || ir[7:0]==`SUB_ABSX || ir[7:0]==`SUB_IMM8 || ir[7:0]==`SUB_IMM16 || ir[7:0]==`SUB_IMM32;
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ir9==`SUB_ABS || ir9==`SUB_ABSX || ir9==`SUB_IMM8 || ir9==`SUB_IMM16 || ir9==`SUB_IMM32;
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isSub8 <= ir[7:0]==`SBC_ZP || ir[7:0]==`SBC_ZPX || ir[7:0]==`SBC_IX || ir[7:0]==`SBC_IY || ir[7:0]==`SBC_I ||
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isSub8 <= ir9==`SBC_ZP || ir9==`SBC_ZPX || ir9==`SBC_IX || ir9==`SBC_IY || ir9==`SBC_I ||
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ir[7:0]==`SBC_ABS || ir[7:0]==`SBC_ABSX || ir[7:0]==`SBC_ABSY || ir[7:0]==`SBC_IMM;
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ir9==`SBC_ABS || ir9==`SBC_ABSX || ir9==`SBC_ABSY || ir9==`SBC_IMM;
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isRMW <= em ? isRMW8 : isRMW32;
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isRMW <= em ? isRMW8 : isRMW32;
|
isOrb <= ir[7:0]==`ORB_ZPX || ir[7:0]==`ORB_IX || ir[7:0]==`ORB_IY || ir[7:0]==`ORB_ABS || ir[7:0]==`ORB_ABSX;
|
isOrb <= ir9==`ORB_ZPX || ir9==`ORB_IX || ir9==`ORB_IY || ir9==`ORB_ABS || ir9==`ORB_ABSX;
|
isStb <= ir[7:0]==`STB_ZPX || ir[7:0]==`STB_ABS || ir[7:0]==`STB_ABSX;
|
isStb <= ir9==`STB_ZPX || ir9==`STB_ABS || ir9==`STB_ABSX;
|
isRTI <= ir[7:0]==`RTI;
|
isRTI <= ir9==`RTI;
|
isRTL <= ir[7:0]==`RTL;
|
isRTL <= ir9==`RTL;
|
isRTS <= ir[7:0]==`RTS;
|
isRTS <= ir9==`RTS;
|
isBrk <= ir[7:0]==`BRK;
|
isBrk <= ir9==`BRK;
|
isMove <= ir[7:0]==`MVP || ir[7:0]==`MVN;
|
isMove <= ir9==`MVP || ir9==`MVN;
|
isSts <= ir[7:0]==`STS;
|
isSts <= ir9==`STS;
|
|
isJsrIndx <= ir9==`JSR_INDX;
|
|
isJsrInd <= ir9==`JSR_IND;
|
|
ldMuldiv <= ir9==`MUL_IMM8 || ir9==`DIV_IMM8 || ir9==`MOD_IMM8 || (ir9==`RR && (
|
|
ir[23:20]==`MUL_RR || ir[23:20]==`MULS_RR || ir[23:20]==`DIV_RR || ir[23:20]==`DIVS_RR || ir[23:20]==`MOD_RR || ir[23:20]==`MODS_RR));
|
|
isPusha <= ir9==`PUSHA;
|
|
isPopa <= ir9==`POPA;
|
end
|
end
|
|
else
|
|
ldMuldiv <= 1'b0;
|
|
|
`ifdef SUPPORT_EXEC
|
`ifdef SUPPORT_EXEC
|
wire isExec = ir[7:0]==`EXEC;
|
wire isExec = ir9==`EXEC;
|
wire isAtni = ir[7:0]==`ATNI;
|
wire isAtni = ir9==`ATNI;
|
`else
|
`else
|
wire isExec = 1'b0;
|
wire isExec = 1'b0;
|
wire isAtni = 1'b0;
|
wire isAtni = 1'b0;
|
`endif
|
`endif
|
wire ld_muldiv = state==DECODE && ir[7:0]==`RR;
|
|
wire md_done;
|
wire md_done;
|
wire clk;
|
wire clk;
|
reg isIY;
|
reg isIY;
|
|
|
rtf65002_pcinc upci1
|
rtf65002_pcinc upci1
|
(
|
(
|
.opcode(ir[7:0]),
|
.opcode(ir9),
|
.suppress_pcinc(suppress_pcinc),
|
.suppress_pcinc(suppress_pcinc),
|
.inc(pc_inc)
|
.inc(pc_inc)
|
);
|
);
|
|
|
|
rtf65002_pcinc8 upci2
|
|
(
|
|
.opcode(ir[7:0]),
|
|
.suppress_pcinc(suppress_pcinc),
|
|
.inc(pc_inc8)
|
|
);
|
|
|
mult_div umd1
|
mult_div umd1
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk),
|
.clk(clk),
|
.ld(ld_muldiv),
|
.ld(ldMuldiv),
|
.op(ir[23:20]),
|
.op(ir9),
|
.a(rfoa),
|
.fn(ir[23:20]),
|
.b(rfob),
|
.a(a),
|
|
.b(b),
|
.p(prod),
|
.p(prod),
|
.q(q),
|
.q(q),
|
.r(r),
|
.r(r),
|
.done(md_done)
|
.done(md_done)
|
);
|
);
|
|
|
`ifdef SUPPORT_ICACHE
|
`ifdef SUPPORT_ICACHE
|
|
`ifdef ICACHE_2WAY
|
|
rtf65002_icachemem2way icm0 (
|
|
.whichrd(whichrd),
|
|
.whichwr(whichwr),
|
|
.wclk(clk),
|
|
.wr(ack_i & isInsnCacheLoad),
|
|
.adr(adr_o),
|
|
.dat(dat_i),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.insn(insn)
|
|
);
|
|
|
|
rtf65002_itagmem2way tgm0 (
|
|
.whichrd(whichrd),
|
|
.whichwr(isCacheReset ? adr_o[13]: whichwr),
|
|
.wclk(clk),
|
|
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
|
|
.adr({adr_o[31:1],!isCacheReset}),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.hit0(hit0),
|
|
.hit1(hit1)
|
|
);
|
|
`else
|
|
`ifdef ICACHE_4K
|
|
rtf65002_icachemem4k icm0 (
|
|
.wclk(clk),
|
|
.wr(ack_i & isInsnCacheLoad),
|
|
.adr(adr_o),
|
|
.dat(dat_i),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.insn(insn)
|
|
);
|
|
|
|
rtf65002_itagmem4k tgm0 (
|
|
.wclk(clk),
|
|
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
|
|
.adr({adr_o[31:1],!isCacheReset}),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.hit0(hit0),
|
|
.hit1(hit1)
|
|
);
|
|
`endif
|
|
`ifdef ICACHE_8K
|
|
rtf65002_icachemem8k icm0 (
|
|
.wclk(clk),
|
|
.wr(ack_i & isInsnCacheLoad),
|
|
.adr(adr_o),
|
|
.dat(dat_i),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.insn(insn)
|
|
);
|
|
|
|
rtf65002_itagmem8k tgm0 (
|
|
.wclk(clk),
|
|
.wr((ack_i & isInsnCacheLoad)|isCacheReset),
|
|
.adr({adr_o[31:1],!isCacheReset}),
|
|
.rclk(~clk),
|
|
.pc(pc),
|
|
.hit0(hit0),
|
|
.hit1(hit1)
|
|
);
|
|
`endif
|
|
`ifdef ICACHE_16K
|
rtf65002_icachemem icm0 (
|
rtf65002_icachemem icm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(ack_i & isInsnCacheLoad),
|
.wr(ack_i & isInsnCacheLoad),
|
.adr(adr_o),
|
.adr(adr_o),
|
.dat(dat_i),
|
.dat(dat_i),
|
| Line 342... |
Line 415... |
.rclk(~clk),
|
.rclk(~clk),
|
.pc(pc),
|
.pc(pc),
|
.hit0(hit0),
|
.hit0(hit0),
|
.hit1(hit1)
|
.hit1(hit1)
|
);
|
);
|
|
`endif
|
|
`endif // ICACHE_2WAY
|
|
|
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
|
wire ihit = (hit0 & hit1);//(pc[2:0] > 3'd1 ? hit1 : 1'b1));
|
`else
|
`else
|
wire ihit = 1'b0;
|
wire ihit = 1'b0;
|
`endif
|
`endif
|
|
|
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
|
assign wr = state==STORE2 && dhit && ack_i;
|
|
|
rtf65002_dcachemem dcm0 (
|
rtf65002_dcachemem dcm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.sel(wr ? wrsel : sel_o),
|
.sel(sel_o),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.wadr(adr_o[33:2]),
|
.wdat(wr ? wdat : dat_i),
|
.wdat(wr ? dat_o : dat_i),
|
.rclk(~clk),
|
.rclk(~clk),
|
.radr(radr),
|
.radr(radr),
|
.rdat(rdat)
|
.rdat(rdat)
|
);
|
);
|
|
|
rtf65002_dtagmem dtm0 (
|
rtf65002_dtagmem dtm0 (
|
.wclk(clk),
|
.wclk(clk),
|
.wr(wr | (ack_i & isDataCacheLoad)),
|
.wr(wr | (ack_i & isDataCacheLoad) | isCacheReset),
|
.wadr(wr ? wadr : adr_o[33:2]),
|
.wadr(adr_o[33:2]),
|
|
.cr(!isCacheReset),
|
.rclk(~clk),
|
.rclk(~clk),
|
.radr(radr),
|
.radr(radr),
|
.hit(dhit)
|
.hit(dhit)
|
);
|
);
|
`endif
|
`endif
|
| Line 416... |
Line 494... |
2'd1: rdat8 <= rdat[15:8];
|
2'd1: rdat8 <= rdat[15:8];
|
2'd2: rdat8 <= rdat[23:16];
|
2'd2: rdat8 <= rdat[23:16];
|
2'd3: rdat8 <= rdat[31:24];
|
2'd3: rdat8 <= rdat[31:24];
|
endcase
|
endcase
|
|
|
|
// Evaluate branches
|
|
//
|
reg takb;
|
reg takb;
|
always @(ir or cf or vf or nf or zf)
|
always @(ir9 or cf or vf or nf or zf)
|
case(ir[7:0])
|
case(ir9)
|
`BEQ: takb <= zf;
|
`BEQ: takb <= zf;
|
`BNE: takb <= !zf;
|
`BNE: takb <= !zf;
|
`BPL: takb <= !nf;
|
`BPL: takb <= !nf;
|
`BMI: takb <= nf;
|
`BMI: takb <= nf;
|
`BCS: takb <= cf;
|
`BCS: takb <= cf;
|
| Line 435... |
Line 515... |
`BLS: takb <= !cf | zf;
|
`BLS: takb <= !cf | zf;
|
`BGE: takb <= (nf & vf)|(!nf & !vf);
|
`BGE: takb <= (nf & vf)|(!nf & !vf);
|
`BLT: takb <= (nf & !vf)|(!nf & vf);
|
`BLT: takb <= (nf & !vf)|(!nf & vf);
|
`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
|
`BGT: takb <= (nf & vf & !zf) + (!nf & !vf & !zf);
|
`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
|
`BLE: takb <= zf | (nf & !vf)|(!nf & vf);
|
//`BAZ: takb <= acc8==8'h00;
|
|
//`BXZ: takb <= x8==8'h00;
|
|
default: takb <= 1'b0;
|
default: takb <= 1'b0;
|
endcase
|
endcase
|
|
|
wire [31:0] zp_address = {abs8[31:12],4'h0,ir[15:8]};
|
wire [31:0] iapy8 = ia + y8; // Don't add in abs8, already included with ia
|
wire [31:0] zpx_address = {abs8[31:12],4'h0,ir[15:8]} + x8;
|
wire [31:0] zp_address = {abs8[31:16],8'h00,ir[15:8]};
|
wire [31:0] zpy_address = {abs8[31:12],4'h0,ir[15:8]} + y8;
|
wire [31:0] zpx_address = {abs8[31:16],8'h00,ir[15:8]} + x8;
|
wire [31:0] abs_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8]};
|
wire [31:0] zpy_address = {abs8[31:16],8'h00,ir[15:8]} + y8;
|
wire [31:0] absx_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
|
wire [31:0] abs_address = {abs8[31:16],ir[23:8]};
|
wire [31:0] absy_address = {abs8[31:12],12'h00} + {16'h0,ir[23:8] + {8'h0,y8}};
|
wire [31:0] absx_address = {abs8[31:16],ir[23:8] + {8'h0,x8}}; // simulates 64k bank wrap-around
|
|
wire [31:0] absy_address = {abs8[31:16],ir[23:8] + {8'h0,y8}};
|
wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
|
wire [31:0] zpx32xy_address = ir[23:12] + rfoa;
|
wire [31:0] absx32xy_address = ir[47:16] + rfob;
|
wire [31:0] absx32xy_address = ir[47:16] + rfob;
|
wire [31:0] zpx32_address = ir[31:20] + rfob;
|
wire [31:0] zpx32_address = ir[31:20] + rfob;
|
wire [31:0] absx32_address = ir[55:24] + rfob;
|
wire [31:0] absx32_address = ir[55:24] + rfob;
|
|
|
reg [32:0] calc_res;
|
rtf65002_alu ualu1
|
always @(a or b or b8 or x or y or df or cf or Rt or shlo or shro)
|
(
|
begin
|
.clk(clk),
|
case(ir[7:0])
|
.state(state),
|
`RR:
|
.resin(res),
|
case(ir[23:20])
|
.pg2(pg2),
|
`ASL_RRR: calc_res <= shlo;
|
.ir(ir),
|
`LSR_RRR: calc_res <= shro;
|
.acc(acc),
|
default: calc_res <= 33'd0;
|
.x(x),
|
endcase
|
.y(y),
|
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: calc_res <= a + b + {31'b0,df&cf};
|
.isp(isp),
|
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: calc_res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
|
.rfoa(rfoa),
|
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: calc_res <= a & b; // Also BIT
|
.rfob(rfob),
|
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: calc_res <= a | b; // Also LD
|
.a(a),
|
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: calc_res <= a ^ b;
|
.b(b),
|
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: calc_res <= b;
|
.b8(b8),
|
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: calc_res <= b;
|
.Rt(Rt),
|
`CPX_ZPX,`CPX_ABS: calc_res <= x - b;
|
.icacheOn(icacheOn),
|
`CPY_ZPX,`CPY_ABS: calc_res <= y - b;
|
.dcacheOn(dcacheOn),
|
`ASL_IMM8: calc_res <= shlo;
|
.write_allocate(write_allocate),
|
`LSR_IMM8: calc_res <= shro;
|
.prod(prod),
|
`ASL_ZPX,`ASL_ABS,`ASL_ABSX: calc_res <= {b,1'b0};
|
.tick(tick),
|
`ROL_ZPX,`ROL_ABS,`ROL_ABSX: calc_res <= {b,cf};
|
.lfsr(lfsr),
|
`LSR_ZPX,`LSR_ABS,`LSR_ABSX: calc_res <= {b[0],1'b0,b[31:1]};
|
.abs8(abs8),
|
`ROR_ZPX,`ROR_ABS,`ROR_ABSX: calc_res <= {b[0],cf,b[31:1]};
|
.vbr(vbr),
|
`INC_ZPX,`INC_ABS,`INC_ABSX: calc_res <= b + 32'd1;
|
.nmoi(nmoi),
|
`DEC_ZPX,`DEC_ABS,`DEC_ABSX: calc_res <= b - 32'd1;
|
.derr_address(derr_address),
|
`ORB_ZPX,`ORB_ABS,`ORB_ABSX: calc_res <= a | {24'h0,b8};
|
.history_buf(history_buf[history_ndx]),
|
default: calc_res <= 33'd0;
|
.spage(spage),
|
endcase
|
.sp(sp),
|
end
|
.df(df),
|
|
.cf(cf),
|
|
.res(alu_out)
|
|
);
|
|
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Clock control
|
// Clock control
|
// - reset or NMI reenables the clock
|
// - reset or NMI reenables the clock
|
| Line 521... |
Line 603... |
adr_o <= 34'd0;
|
adr_o <= 34'd0;
|
dat_o <= 32'd0;
|
dat_o <= 32'd0;
|
nmi_edge <= 1'b0;
|
nmi_edge <= 1'b0;
|
wai <= 1'b0;
|
wai <= 1'b0;
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
|
wr <= 1'b0;
|
|
cf <= 1'b0;
|
cf <= 1'b0;
|
ir <= 64'hEAEAEAEAEAEAEAEA;
|
ir <= 64'hEAEAEAEAEAEAEAEA;
|
imiss <= `FALSE;
|
imiss <= `FALSE;
|
dmiss <= `FALSE;
|
dmiss <= `FALSE;
|
dcacheOn <= 1'b0;
|
dcacheOn <= 1'b0;
|
icacheOn <= 1'b1;
|
icacheOn <= 1'b1;
|
write_allocate <= 1'b0;
|
write_allocate <= 1'b0;
|
nmoi <= 1'b1;
|
nmoi <= 1'b1;
|
state <= RESET1;
|
state <= RESET1;
|
cstate <= IDLE;
|
|
if (rst_md) begin
|
if (rst_md) begin
|
pc <= 32'h0000FFF0; // set high-order pc to zero
|
pc <= 32'h0000FFF0; // set high-order pc to zero
|
vect <= `BYTE_RST_VECT;
|
vect <= `BYTE_RST_VECT;
|
em <= 1'b1;
|
em <= 1'b1;
|
end
|
end
|
| Line 555... |
Line 635... |
tick <= 32'd0;
|
tick <= 32'd0;
|
isIY <= 1'b0;
|
isIY <= 1'b0;
|
load_what <= `NOTHING;
|
load_what <= `NOTHING;
|
hist_capture <= `TRUE;
|
hist_capture <= `TRUE;
|
history_ndx <= 6'd0;
|
history_ndx <= 6'd0;
|
|
pg2 <= `FALSE;
|
|
tf <= `FALSE;
|
|
km <= `TRUE;
|
end
|
end
|
else begin
|
else begin
|
tick <= tick + 32'd1;
|
tick <= tick + 32'd1;
|
wr <= 1'b0;
|
|
if (nmi_i & !nmi1)
|
if (nmi_i & !nmi1)
|
nmi_edge <= 1'b1;
|
nmi_edge <= 1'b1;
|
if (nmi_i|nmi1)
|
if (nmi_i|nmi1)
|
clk_en <= 1'b1;
|
clk_en <= 1'b1;
|
case(state)
|
case(state)
|
|
// Loop in this state until all the cache address tage have been flagged as
|
|
// invalid.
|
|
//
|
RESET1:
|
RESET1:
|
begin
|
begin
|
adr_o <= adr_o + 32'd4;
|
adr_o <= adr_o + 32'd4;
|
if (adr_o[13:4]==10'h3FF) begin
|
if (adr_o[13:4]==10'h3FF) begin
|
state <= RESET2;
|
state <= RESET2;
|
| Line 581... |
Line 666... |
load_what <= em ? `PC_70 : `PC_310;
|
load_what <= em ? `PC_70 : `PC_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
|
`include "ifetch.v"
|
`include "ifetch.v"
|
`include "decode.v"
|
|
`ifdef SUPPORT_EM8
|
`ifdef SUPPORT_EM8
|
|
`include "byte_ifetch.v"
|
`include "byte_decode.v"
|
`include "byte_decode.v"
|
`include "byte_calc.v"
|
`include "byte_calc.v"
|
`include "byte_jsr.v"
|
|
`include "byte_jsl.v"
|
|
`ifdef SUPPORT_BYTE_IRQ
|
|
`include "byte_irq.v"
|
|
`endif
|
|
`endif
|
`endif
|
|
|
`include "load_mac.v"
|
`include "load_mac.v"
|
`include "store.v"
|
`include "store.v"
|
|
|
|
// This state waits for a data hit before continuing. It's used after a store
|
|
// operation when write allocation is taking place.
|
WAIT_DHIT:
|
WAIT_DHIT:
|
if (dhit)
|
if (dhit)
|
state <= retstate;
|
state <= retstate;
|
|
|
`include "calc.v"
|
DECODE: decode_tsk();
|
|
CALC: calc_tsk();
|
JSR_INDX1:
|
|
if (ack_i) begin
|
|
load_what <= `PC_310;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
adr_o <= 34'd0;
|
|
dat_o <= 32'd0;
|
|
radr <= ir[39:8] + x;
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
|
end
|
|
|
|
JSR161:
|
MULDIV1: state <= MULDIV2;
|
if (ack_i) begin
|
MULDIV2:
|
state <= IFETCH;
|
|
retstate <= IFETCH;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
pc <= {{16{ir[23]}},ir[23:8]};
|
|
isp <= isp_dec;
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
end
|
|
/*
|
|
IRQ0:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
adr_o <= {wadr,2'b00};
|
|
dat_o <= wdat;
|
|
state <= IRQ1;
|
|
end
|
|
IRQ1:
|
|
if (ack_i) begin
|
|
ir <= 64'd0; // Force instruction decoder to BRK
|
|
state <= IRQ2;
|
|
retstate <= IRQ2;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
isp <= isp_dec;
|
|
`ifdef SUPPORT_DCACHE
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
state <= WAIT_DHIT;
|
|
dmiss <= `TRUE;
|
|
end
|
|
`endif
|
|
end
|
|
IRQ2:
|
|
begin
|
|
cyc_o <= 1'b1;
|
|
stb_o <= 1'b1;
|
|
we_o <= 1'b1;
|
|
sel_o <= 4'hF;
|
|
radr <= isp_dec;
|
|
wadr <= isp_dec;
|
|
wdat <= sr;
|
|
adr_o <= {isp_dec,2'b00};
|
|
dat_o <= sr;
|
|
state <= IRQ3;
|
|
end
|
|
IRQ3:
|
|
if (ack_i) begin
|
|
load_what <= `PC_310;
|
|
state <= LOAD_MAC1;
|
|
retstate <= LOAD_MAC1;
|
|
cyc_o <= 1'b0;
|
|
stb_o <= 1'b0;
|
|
we_o <= 1'b0;
|
|
sel_o <= 4'h0;
|
|
isp <= isp_dec;
|
|
`ifdef SUPPORT_DCACHE
|
|
if (dhit) begin
|
|
wrsel <= sel_o;
|
|
wr <= 1'b1;
|
|
end
|
|
else if (write_allocate) begin
|
|
dmiss <= `TRUE;
|
|
state <= WAIT_DHIT;
|
|
end
|
|
`endif
|
|
radr <= vect[31:2];
|
|
if (hwi)
|
|
im <= 1'b1;
|
|
em <= 1'b0; // make sure we process in native mode; we might have been called up during emulation mode
|
|
end
|
|
*/
|
|
MULDIV1:
|
|
if (md_done) begin
|
if (md_done) begin
|
state <= IFETCH;
|
state <= IFETCH;
|
|
case(ir9)
|
|
`RR:
|
case(ir[23:20])
|
case(ir[23:20])
|
`MUL_RR: begin res <= prod[31:0]; end
|
`MUL_RR: begin res <= prod[31:0]; end
|
`MULS_RR: begin res <= prod[31:0]; end
|
`MULS_RR: begin res <= prod[31:0]; end
|
|
`ifdef SUPPORT_DIVMOD
|
`DIV_RR: begin res <= q; end
|
`DIV_RR: begin res <= q; end
|
`DIVS_RR: begin res <= q; end
|
`DIVS_RR: begin res <= q; end
|
`MOD_RR: begin res <= r; end
|
`MOD_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
`MODS_RR: begin res <= r; end
|
|
`endif
|
|
endcase
|
|
`MUL_IMM8,`MUL_IMM16,`MUL_IMM32: res <= prod[31:0];
|
|
`ifdef SUPPORT_DIVMOD
|
|
`DIV_IMM8,`DIV_IMM16,`DIV_IMM32: res <= q;
|
|
`MOD_IMM8,`MOD_IMM16,`MOD_IMM32: res <= r;
|
|
`endif
|
endcase
|
endcase
|
end
|
end
|
|
|
`ifdef SUPPORT_BERR
|
`ifdef SUPPORT_BERR
|
BUS_ERROR:
|
BUS_ERROR:
|
begin
|
begin
|
|
pg2 <= `FALSE;
|
|
ir <= {8{`BRK}};
|
|
hist_capture <= `FALSE;
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
wdat <= opc;
|
isp <= isp_dec;
|
|
store_what <= `STW_OPC;
|
if (em | isOrb | isStb)
|
if (em | isOrb | isStb)
|
derr_address <= adr_o[31:0];
|
derr_address <= adr_o[31:0];
|
else
|
else
|
derr_address <= adr_o[33:2];
|
derr_address <= adr_o[33:2];
|
vect <= {vbr[31:9],9'd508,2'b00};
|
vect <= {vbr[31:9],9'd508,2'b00};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
state <= IRQ0;
|
isBusErr <= `TRUE;
|
|
state <= STORE1;
|
end
|
end
|
INSN_BUS_ERROR:
|
INSN_BUS_ERROR:
|
begin
|
begin
|
|
pg2 <= `FALSE;
|
|
ir <= {8{`BRK}};
|
|
hist_capture <= `FALSE;
|
radr <= isp_dec;
|
radr <= isp_dec;
|
wadr <= isp_dec;
|
wadr <= isp_dec;
|
wdat <= opc;
|
isp <= isp_dec;
|
|
store_what <= `STW_OPC;
|
|
derr_address <= 34'd0;
|
vect <= {vbr[31:9],9'd509,2'b00};
|
vect <= {vbr[31:9],9'd509,2'b00};
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
state <= IRQ0;
|
isBusErr <= `TRUE;
|
end
|
|
`endif
|
|
|
|
`ifdef SUPPORT_STRING
|
|
MVN1:
|
|
begin
|
|
radr <= x;
|
|
res <= x + 32'd1;
|
|
retstate <= MVN2;
|
|
load_what <= `WORD_312;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
MVN2:
|
|
begin
|
|
radr <= y;
|
|
wadr <= y;
|
|
store_what <= `STW_B;
|
|
x <= res;
|
|
res <= y + 32'd1;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
|
end
|
|
MVN3:
|
|
begin
|
|
state <= IFETCH;
|
|
y <= res;
|
|
if (acc==32'hFFFFFFFF)
|
|
pc <= pc + 32'd1;
|
|
end
|
|
MVP1:
|
|
begin
|
|
radr <= x;
|
|
res <= x - 32'd1;
|
|
retstate <= MVP2;
|
|
load_what <= `WORD_312;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
MVP2:
|
|
begin
|
|
radr <= y;
|
|
wadr <= y;
|
|
store_what <= `STW_B;
|
|
x <= res;
|
|
res <= y - 32'd1;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
|
end
|
|
STS1:
|
|
begin
|
|
radr <= y;
|
|
wadr <= y;
|
|
store_what <= `STW_X;
|
|
res <= y + 32'd1;
|
|
acc <= acc - 32'd1;
|
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`endif
|
`endif
|
|
|
endcase
|
`include "rtf65002_string.v"
|
|
|
`include "cache_controller.v"
|
`include "cache_controller.v"
|
|
|
|
endcase
|
end
|
end
|
|
`include "decode.v"
|
|
`include "calc.v"
|
|
`include "load_tsk.v"
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
