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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [BRANCH.v] - Diff between revs 2 and 7

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Rev 2 Rev 7
Line 5... Line 5...
//  - fetch an 8 bit displacement and add into IP
//  - fetch an 8 bit displacement and add into IP
//
//
//
//
//  (C) 2009-2012 Robert Finch
//  (C) 2009-2012 Robert Finch
//  Stratford
//  Stratford
//  robfinch<remove>@opencores.org
//  robfinch<remove>@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
Line 28... Line 28...
//
//
// Fetch branch displacement if taking branch, otherwise skip
// Fetch branch displacement if taking branch, otherwise skip
//
//
BRANCH1:
BRANCH1:
        if (take_br) begin
        if (take_br) begin
                `INITIATE_CODE_READ
                code_read();
                state <= BRANCH2;
                state <= BRANCH2;
        end
        end
        else begin
        else begin
                ip <= ip_inc;
                ip <= ip_inc;
                state <= IFETCH;
                state <= IFETCH;
        end
        end
BRANCH2:
BRANCH2:
        if (ack_i) begin
        if (ack_i) begin
                `TERMINATE_CODE_READ
                term_code_read();
                disp16 <= {{8{dat_i[7]}},dat_i};
                disp16 <= {{8{dat_i[7]}},dat_i};
                state <= BRANCH3;
                state <= BRANCH3;
        end
        end
BRANCH3:
BRANCH3:
        begin
        begin

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