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[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [CALL.v] - Diff between revs 2 and 7

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//=============================================================================
//=============================================================================
//  CALL NEAR
//  CALL NEAR
//
//
//
//
//  2009-2012 Robert Finch
//  2009-2013 Robert Finch
//  Stratford
//  Stratford
//  robfinch<remove>@opencores.org
//  robfinch<remove>@finitron.ca
//
//
//
//
// This source file is free software: you can redistribute it and/or modify 
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// by the Free Software Foundation, either version 3 of the License, or     
Line 23... Line 23...
//
//
//=============================================================================
//=============================================================================
//
//
CALL:
CALL:
        begin
        begin
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,ip[15:8]);
                lock_o <= 1'b1;
                lock_o <= 1'b1;
                dat_o <= ip[15:8];
 
                state <= CALL1;
                state <= CALL1;
        end
        end
CALL1:
CALL1:
        if (ack_i) begin
        if (ack_i) begin
                state <= CALL2;
                state <= CALL2;
                `PAUSE_STACK_WRITE
                pause_stack_push();
        end
        end
CALL2:
CALL2:
        begin
        begin
                state <= CALL3;
                state <= CALL3;
                `INITIATE_STACK_WRITE
                write(`CT_WRMEM,sssp,ip[7:0]);
                dat_o <= ip[7:0];
 
        end
        end
CALL3:
CALL3:
        if (ack_i) begin
        if (ack_i) begin
                `TERMINATE_CYCLE
                nack();
                lock_o <= 1'b0;
                lock_o <= 1'b0;
                ip <= ip + disp16;
                ip <= ip + disp16;
                state <= IFETCH;
                state <= IFETCH;
        end
        end
 
 
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