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Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [EXECUTE.v] - Diff between revs 5 and 6

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Rev 5 Rev 6
Line 98... Line 98... 
                                zf <= resz;
 
                                zf <= resz;
 
                        end
 
                        end
 
 
 
 
 
                8'hF6,8'hF7:
 
                8'hF6,8'hF7:
 
                        begin
 
                        begin
 
                                wrregs <= 1'b1;
 
 
 
                                state <= IFETCH;
 
                                state <= IFETCH;
 
                                case(rrr)
 
                                res <= alu_o;
 
                                3'd2: res <= ~b;        // NOT
 
                                case(TTT)
 
                                3'd3: res <= -b;        // NEG
 
                                3'd0:   // TEST
 
 
 
                                        begin
 
 
 
                                                pf <= pres;
 
 
 
                                                cf <= 1'b0;
 
 
 
                                                vf <= 1'b0;
 
 
 
                                                sf <= resn;
 
 
 
                                                zf <= resz;
 
 
 
                                        end
 
 
 
                                3'd2:   // NOT
 
 
 
                                        begin
 
 
 
                                                wrregs <= 1'b1;
 
 
 
                                        end
 
 
 
                                3'd3:   // NEG
 
 
 
                                        begin
 
 
 
                                                pf <= pres;
 
 
 
                                                af <= carry   (1'b1,1'b0,b[3],alu_o[3]);
 
 
 
                                                cf <= carry   (1'b1,1'b0,bmsb,resn);
 
 
 
                                                vf <= overflow(1'b1,1'b0,bmsb,resn);
 
 
 
                                                sf <= resn;
 
 
 
                                                zf <= resz;
 
 
 
                                                wrregs <= 1'b1;
 
 
 
                                        end
 
 
 
                                // Normally only a single register update is required, however with 
 
 
                                // multiply word both AX and DX need to be updated. So we bypass the
 
 
 
                                // regular update here.
 
 
 
                                3'd4:
 
 
 
                                        begin
 
 
 
                                                if (w) begin
 
 
 
                                                        ax <= p32[15:0];
 
 
 
                                                        dx <= p32[31:16];
 
 
 
                                                        cf <= p32[31:16]!=16'd0;
 
 
 
                                                        vf <= p32[31:16]!=16'd0;
 
 
 
                                                end
 
 
 
                                                else begin
 
 
 
                                                        ax <= p16;
 
 
 
                                                        cf <= p16[15:8]!=8'd0;
 
 
 
                                                        vf <= p16[15:8]!=8'd0;
 
 
 
                                                end
 
 
 
                                        end
 
 
 
                                3'd5:
 
 
 
                                        begin
 
 
 
                                                if (w) begin
 
 
 
                                                        ax <= wp[15:0];
 
 
 
                                                        dx <= wp[31:16];
 
 
 
                                                        cf <= p32[31:16]!=16'd0;
 
 
 
                                                        vf <= p32[31:16]!=16'd0;
 
 
 
                                                end
 
 
 
                                                else begin
 
 
 
                                                        ax <= p;
 
 
 
                                                        cf <= p[15:8]!=8'd0;
 
 
 
                                                        vf <= p[15:8]!=8'd0;
 
 
 
                                                end
 
 
 
                                        end
 
 
 
                                3'd6,3'd7:
 
 
 
                                        begin
 
 
 
                                                state <= DIVIDE1;
 
 
 
                                        end
 
 
 
                                default:        ;
 
                                endcase
 
                                endcase
 
                        end
 
                        end
 
 
 
 
 
                `INC_REG:
 
                `INC_REG:
 
                        begin
 
                        begin
 
                                state <= IFETCH;
 
                                state <= IFETCH;
 
                                wrregs <= 1'b1;
 
                                wrregs <= 1'b1;
 
                                w <= 1'b1;
 
                                w <= 1'b1;
Line 280... Line 337... 
                                                        cf <= b[0];
 
                                                        cf <= b[0];
 
                                                        vf <= cf^b[15];
 
                                                        vf <= cf^b[15];
 
                                                end
 
                                                end
 
                                        3'b100: // SHL
 
                                        3'b100: // SHL
 
                                                begin
 
                                                begin
 
                                                        $display("SHL:%h,%h,%d",shlo[15:0],b,shftamt);
 
 
 
                                                        res <= shlo[15:0];
 
                                                        res <= shlo[15:0];
 
                                                        cf <= shlo[16];
 
                                                        cf <= shlo[16];
 
                                                        vf <= b[15]^b[14];
 
                                                        vf <= b[15]^b[14];
 
                                                end
 
                                                end
 
                                        3'b101: // SHR
 
                                        3'b101: // SHR
 
                                                begin
 
                                                begin
 
                                                        $display("SHR:%h,%h,%d",shruo[31:16],b,shftamt);
 
 
 
                                                        res <= shruo[31:16];
 
                                                        res <= shruo[31:16];
 
                                                        cf <= shruo[15];
 
                                                        cf <= shruo[15];
 
                                                        vf <= b[15];
 
                                                        vf <= b[15];
 
                                                end
 
                                                end
 
                                        3'b111: // SAR
 
                                        3'b111: // SAR

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