URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

[/] [rtf8088/] [trunk/] [rtl/] [verilog/] [LODS.v] - Diff between revs 2 and 8

Rev 2	Rev 8
Line 1...	Line 1...
`//=============================================================================`	`//=============================================================================`
`// LODS`	`// LODS`
`// Fetch string data from memory.`	`// Fetch string data from memory.`
`//`	`//`
`//`	`//`
`// 2009,2010 Robert Finch`	`// 2009,2010,2013 Robert Finch`
`// Stratford`	`// Stratford`
`// robfinch<remove>@opencores.org`	`// robfinch<remove>@finitron.ca`
`//`	`//`
`//`	`//`
`// This source file is free software: you can redistribute it and/or modify`	`// This source file is free software: you can redistribute it and/or modify`
`// it under the terms of the GNU Lesser General Public License as published`	`// it under the terms of the GNU Lesser General Public License as published`
`// by the Free Software Foundation, either version 3 of the License, or`	`// by the Free Software Foundation, either version 3 of the License, or`
Line 25...	Line 25...
`//`	`//`
`LODS:`	`LODS:`
`if (w && (si==16'hFFFF) && !df) begin`	`if (w && (si==16'hFFFF) && !df) begin`
ir <= `NOP;	ir <= `NOP;
`int_num <= 8'd13;`	`int_num <= 8'd13;`
`state <= INT1;`	`state <= INT2;`
`end`	`end`
`else begin`	`else begin`
cyc_type <= `CT_RDMEM;	cyc_type <= `CT_RDMEM;
`lock_o <= w;`	`lock_o <= w;`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`