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[/] [rtfbitmapcontroller/] [trunk/] [rtl/] [verilog/] [rtfBitmapController5.v] - Diff between revs 23 and 24

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`// Bitmap Controller (Frame Buffer Display)`	`// Bitmap Controller (Frame Buffer Display)`
`// - Displays a bitmap from memory.`	`// - Displays a bitmap from memory.`
`//`	`//`
`//`	`//`
`// __`	`// __`
`// \\__/ o\ (C) 2008-2018 Robert Finch, Waterloo`	`// \\__/ o\ (C) 2008-2019 Robert Finch, Waterloo`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch<remove>@finitron.ca`	`// \/_// robfinch<remove>@finitron.ca`
`// \|\|`	`// \|\|`
`//`	`//`
`//`	`//`
Line 24...	Line 24...
`// You should have received a copy of the GNU General Public License`	`// You should have received a copy of the GNU General Public License`
`// along with this program. If not, see <http://www.gnu.org/licenses/>.`	`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
`//`	`//`
`//`	`//`
`// The default base screen address is:`	`// The default base screen address is:`
`// $0200000 - the second 4MiB of RAM`	`// $0200000 - the third meg of RAM`
`//`	`//`
`//`	`//`
`// Verilog 1995`	`// Verilog 1995`
`//`	`//`
`// ============================================================================`	`// ============================================================================`
Line 37...	Line 37...
`define INTERNAL_SYNC_GEN 1'b1	`define INTERNAL_SYNC_GEN 1'b1

`define ABITS 31:0	`define ABITS 31:0
`define HIGH 1'b1	`define HIGH 1'b1
`define LOW 1'b0	`define LOW 1'b0
	`define TRUE 1'b1
	`define FALSE 1'b0

`module rtfBitmapController5(`	`module rtfBitmapController5(`
`rst_i,`	`rst_i, irq_o,`
`s_clk_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_sel_i, s_adr_i, s_dat_i, s_dat_o, irq_o,`	`s_clk_i, s_cs_i, s_cyc_i, s_stb_i, s_ack_o, s_we_i, s_sel_i, s_adr_i, s_dat_i, s_dat_o,`
`m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, m_dat_o,`	`m_clk_i, m_cyc_o, m_stb_o, m_ack_i, m_we_o, m_sel_o, m_adr_o, m_dat_i, m_dat_o,`
`dot_clk_i, zrgb_o, xonoff_i`	`dot_clk_i, zrgb_o, xonoff_i`
`ifdef INTERNAL_SYNC_GEN	`ifdef INTERNAL_SYNC_GEN
`, hsync_o, vsync_o, blank_o, border_o`	`, hsync_o, vsync_o, blank_o, border_o, hctr_o, vctr_o, fctr_o`
`else	`else
`, hsync_i, vsync_i, blank_i`	`, hsync_i, vsync_i, blank_i`
`endif	`endif
`);`	`);`
	`parameter MDW = 128; // Bus master data width`
`parameter BM_BASE_ADDR1 = 32'h0020_0000;`	`parameter BM_BASE_ADDR1 = 32'h0020_0000;`
`parameter BM_BASE_ADDR2 = 32'h0028_0000;`	`parameter BM_BASE_ADDR2 = 32'h0028_0000;`
`parameter REG_CTRL = 9'd0;`	`parameter REG_CTRL = 9'd0;`
`parameter REG_DISPLAYED = 9'd1;`	`parameter REG_DISPLAYED = 9'd1;`
`parameter REG_PAGE1ADDR = 9'd2;`	`parameter REG_PAGE1ADDR = 9'd2;`
Line 61...	Line 64...
`parameter REG_PCOLCMD = 9'd5;`	`parameter REG_PCOLCMD = 9'd5;`
`parameter REG_TOTAL = 9'd8;`	`parameter REG_TOTAL = 9'd8;`
`parameter REG_SYNC_ONOFF = 9'd9;`	`parameter REG_SYNC_ONOFF = 9'd9;`
`parameter REG_BLANK_ONOFF = 9'd10;`	`parameter REG_BLANK_ONOFF = 9'd10;`
`parameter REG_BORDER_ONOFF = 9'd11;`	`parameter REG_BORDER_ONOFF = 9'd11;`
	`parameter REG_RASTCMP = 9'd12;`

`parameter BPP4 = 3'd0;`	`parameter BPP4 = 3'd0;`
`parameter BPP8 = 3'd1;`	`parameter BPP8 = 3'd1;`
`parameter BPP12 = 3'd2;`	`parameter BPP12 = 3'd2;`
`parameter BPP16 = 3'd3;`	`parameter BPP16 = 3'd3;`
Line 105...	Line 109...
`parameter pvTotal = 628; // 628 total scan lines`	`parameter pvTotal = 628; // 628 total scan lines`


`// SYSCON`	`// SYSCON`
`input rst_i; // system reset`	`input rst_i; // system reset`
	`output irq_o;`

`// Peripheral IO slave port`	`// Peripheral IO slave port`
`input s_clk_i;`	`input s_clk_i;`
`input s_cs_i;`	`input s_cs_i;`
`input s_cyc_i;`	`input s_cyc_i;`
Line 118...	Line 123...
`input [7:0] s_sel_i;`	`input [7:0] s_sel_i;`
`input [11:0] s_adr_i;`	`input [11:0] s_adr_i;`
`input [63:0] s_dat_i;`	`input [63:0] s_dat_i;`
`output [63:0] s_dat_o;`	`output [63:0] s_dat_o;`
`reg [63:0] s_dat_o;`	`reg [63:0] s_dat_o;`
`output irq_o;`

`// Video Memory Master Port`	`// Video Memory Master Port`
`// Used to read memory via burst access`	`// Used to read memory via burst access`
`input m_clk_i; // system bus interface clock`	`input m_clk_i; // system bus interface clock`
`output m_cyc_o; // video burst request`	`output m_cyc_o; // video burst request`
`output m_stb_o;`	`output m_stb_o;`
`output reg m_we_o;`	`output reg m_we_o;`
`output [7:0] m_sel_o;`	`output [MDW/8-1:0] m_sel_o;`
`input m_ack_i; // vid_acknowledge from memory`	`input m_ack_i; // vid_acknowledge from memory`
output [`ABITS] m_adr_o; // address for memory access	output [`ABITS] m_adr_o; // address for memory access
`input [63:0] m_dat_i; // memory data input`	`input [MDW-1:0] m_dat_i; // memory data input`
`output reg [63:0] m_dat_o;`	`output reg [MDW-1:0] m_dat_o;`

`// Video`	`// Video`
`input dot_clk_i; // Video clock 80 MHz`	`input dot_clk_i; // Video clock 80 MHz`
`ifdef INTERNAL_SYNC_GEN	`ifdef INTERNAL_SYNC_GEN
`output hsync_o;`	`output hsync_o;`
`output vsync_o;`	`output vsync_o;`
`output blank_o;`	`output blank_o;`
`output border_o;`	`output border_o;`
	`output [11:0] hctr_o;`
	`output [11:0] vctr_o;`
	`output [5:0] fctr_o;`
`else	`else
`input hsync_i; // start/end of scan line`	`input hsync_i; // start/end of scan line`
`input vsync_i; // start/end of frame`	`input vsync_i; // start/end of frame`
`input blank_i; // blank the output`	`input blank_i; // blank the output`
`endif	`endif
Line 152...	Line 159...
`input xonoff_i;`	`input xonoff_i;`

`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`// IO registers`	`// IO registers`
`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
	`reg irq_o;`
`reg m_cyc_o;`	`reg m_cyc_o;`
`reg [31:0] m_adr_o;`	`reg [31:0] m_adr_o;`

`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`wire cs = s_cyc_i & s_stb_i & s_cs_i;`	`wire vclk;`
`reg ack,ack1;`	`reg cs;`
	`reg we;`
	`reg [7:0] sel;`
	`reg [11:0] adri;`
	`reg [63:0] dat;`

`always @(posedge s_clk_i)`	`always @(posedge s_clk_i)`
`begin`	`cs <= s_cyc_i & s_stb_i & s_cs_i;`
`ack1 <= cs;`	`always @(posedge s_clk_i)`
`ack <= ack1 & cs;`	`we <= s_we_i;`
`end`	`always @(posedge s_clk_i)`
`assign s_ack_o = cs ? (s_we_i ? 1'b1 : ack) : 1'b0;`	`sel <= s_sel_i;`
	`always @(posedge s_clk_i)`
	`adri <= s_adr_i;`
	`always @(posedge s_clk_i)`
	`dat <= s_dat_i;`

	`ack_gen #(`
	`.READ_STAGES(2),`
	`.WRITE_STAGES(0),`
	`.REGISTER_OUTPUT(1)`
	`) uag1`
	`(`
	`.clk_i(s_clk_i),`
	`.ce_i(1'b1),`
	`.i(cs),`
	`.we_i(s_cyc_i & s_stb_i & s_cs_i & s_we_i),`
	`.o(s_ack_o)`
	`);`

`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`integer n;`	`integer n;`
`wire vclk;`
`reg [11:0] hDisplayed,vDisplayed;`	`reg [11:0] hDisplayed,vDisplayed;`
	`reg [11:0] rastcmp;`
reg [`ABITS] bm_base_addr1,bm_base_addr2;	reg [`ABITS] bm_base_addr1,bm_base_addr2;
`reg [2:0] color_depth;`	`reg [2:0] color_depth;`
`wire [7:0] fifo_cnt;`	`wire [7:0] fifo_cnt;`
`reg onoff;`	`reg onoff;`
`reg [2:0] hres,vres;`	`reg [2:0] hres,vres;`
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`reg [11:0] hrefdelay;`	`reg [11:0] hrefdelay;`
`reg [11:0] vrefdelay;`	`reg [11:0] vrefdelay;`
`reg [11:0] map; // memory access period`	`reg [11:0] map; // memory access period`
`reg [11:0] mapctr;`	`reg [11:0] mapctr;`
reg [`ABITS] baseAddr; // base address register	reg [`ABITS] baseAddr; // base address register
`wire [127:0] rgbo1;`	`wire [63:0] rgbo1;`
`reg [11:0] pixelRow;`	`reg [11:0] pixelRow;`
`reg [11:0] pixelCol;`	`reg [11:0] pixelCol;`
`wire [31:0] pal_wo;`	`wire [31:0] pal_wo;`
`wire [31:0] pal_o;`	`wire [31:0] pal_o;`
`reg [11:0] px;`	`reg [11:0] px;`
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`reg [11:0] hBlankOn = phBlankOn, hBlankOff = phBlankOff;`	`reg [11:0] hBlankOn = phBlankOn, hBlankOff = phBlankOff;`
`reg [11:0] vBlankOn = pvBlankOn, vBlankOff = pvBlankOff;`	`reg [11:0] vBlankOn = pvBlankOn, vBlankOff = pvBlankOff;`
`reg [11:0] hBorderOn = phBorderOn, hBorderOff = phBorderOff;`	`reg [11:0] hBorderOn = phBorderOn, hBorderOff = phBorderOff;`
`reg [11:0] vBorderOn = pvBorderOn, vBorderOff = pvBorderOff;`	`reg [11:0] vBorderOn = pvBorderOn, vBorderOff = pvBorderOff;`
`reg sgLock;`	`reg sgLock;`
	`wire pe_hsync, pe_hsync2;`
	`wire pe_vsync;`

`ifdef INTERNAL_SYNC_GEN	`ifdef INTERNAL_SYNC_GEN
`wire hsync_i, vsync_i, blank_i;`	`wire hsync_i, vsync_i, blank_i;`

`VGASyncGen usg1`	`VGASyncGen usg1`
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`.clk(vclk),`	`.clk(vclk),`
`.eol(),`	`.eol(),`
`.eof(),`	`.eof(),`
`.hSync(hsync_o),`	`.hSync(hsync_o),`
`.vSync(vsync_o),`	`.vSync(vsync_o),`
`.hCtr(),`	`.hCtr(hctr_o),`
`.vCtr(),`	`.vCtr(vctr_o),`
`.blank(blank_o),`	`.blank(blank_o),`
`.vblank(vblank),`	`.vblank(vblank),`
`.vbl_int(),`	`.vbl_int(),`
`.border(border_o),`	`.border(border_o),`
`.hTotal_i(hTotal),`	`.hTotal_i(hTotal),`
Line 255...	Line 287...
`.pe(cs_edge),`	`.pe(cs_edge),`
`.ne(),`	`.ne(),`
`.ee()`	`.ee()`
`);`	`);`

	`// Frame counter`
	`//`
	`VT163 #(6) ub1`
	`(`
	`.clk(vclk),`
	`.clr_n(!rst_i),`
	`.ent(pe_vsync),`
	`.enp(1'b1),`
	`.ld_n(1'b1),`
	`.d(6'd0),`
	`.q(fctr_o),`
	`.rco()`
	`);`

	`reg rst_irq;`
	`always @(posedge vclk)`
	`if (rst_i)`
	irq_o <= `LOW;
	`else begin`
	`if (hctr_o==12'd02 && rastcmp==vctr_o)`
	irq_o <= `HIGH;
	`else if (rst_irq)`
	irq_o <= `LOW;
	`end`

`always @(page or bm_base_addr1 or bm_base_addr2)`	`always @(page or bm_base_addr1 or bm_base_addr2)`
`baseAddr = page ? bm_base_addr2 : bm_base_addr1;`	`baseAddr = page ? bm_base_addr2 : bm_base_addr1;`

`// Color palette RAM for 8bpp modes`	`// Color palette RAM for 8bpp modes`
`syncRam512x32_1rw1r upal1`	`syncRam512x32_1rw1r upal1`
`(`	`(`
`.wrst(1'b0),`	`.wrst(1'b0),`
`.wclk(s_clk_i),`	`.wclk(s_clk_i),`
`.wce(cs & s_adr_i[11]),`	`.wce(cs & adri[11]),`
`.we(s_we_i),`	`.we(we),`
`.wadr({2'b0,s_adr_i[9:3]}),`	`.wadr({2'b0,adri[9:3]}),`
`.i(s_dat_i[31:0]),`	`.i(dat[31:0]),`
`.wo(pal_wo),`	`.wo(pal_wo),`
`.rrst(1'b0),`	`.rrst(1'b0),`
`.rclk(vclk),`	`.rclk(vclk),`
`.rce(1'b1),`	`.rce(1'b1),`
`.radr({2'b0,pals,rgbo4[5:0]}),`	`.radr({2'b0,pals,rgbo4[5:0]}),`
Line 291...	Line 347...
`onoff <= 1'b1;`	`onoff <= 1'b1;`
`color_depth <= BPP16;`	`color_depth <= BPP16;`
`greyscale <= 1'b0;`	`greyscale <= 1'b0;`
`bm_base_addr1 <= BM_BASE_ADDR1;`	`bm_base_addr1 <= BM_BASE_ADDR1;`
`bm_base_addr2 <= BM_BASE_ADDR2;`	`bm_base_addr2 <= BM_BASE_ADDR2;`
`hrefdelay <= 12'd154;//12'd218;`	`hrefdelay <= 12'd103;//12'd218;`
`vrefdelay <= 12'd10;//12'd27;`	`vrefdelay <= 12'd13;//12'd27;`
`map <= 12'd0;`	`map <= 12'd0;`
`pcmd <= 2'b00;`	`pcmd <= 2'b00;`
`rstcmd1 <= 1'b0;`	`rstcmd1 <= 1'b0;`
	`rst_irq <= 1'b0;`
	`rastcmp <= 12'hFFF;`
`end`	`end`
`else begin`	`else begin`
`rstcmd1 <= rstcmd;`	`rstcmd1 <= rstcmd;`
	`rst_irq <= 1'b0;`
`if (rstcmd & ~rstcmd1)`	`if (rstcmd & ~rstcmd1)`
`pcmd <= 2'b00;`	`pcmd <= 2'b00;`
`if (cs_edge) begin`	`if (cs_edge) begin`
`if (s_we_i) begin`	`if (we) begin`
`case(s_adr_i[11:3])`	`casez(adri[11:3])`
`REG_CTRL:`	`REG_CTRL:`
`begin`	`begin`
`if (s_sel_i[0]) onoff <= s_dat_i[0];`	`if (sel[0]) onoff <= dat[0];`
`if (s_sel_i[1]) begin`	`if (sel[1]) begin`
`color_depth <= s_dat_i[10:8];`	`color_depth <= dat[10:8];`
`greyscale <= s_dat_i[11];`	`greyscale <= dat[11];`
`end`	`end`
`if (s_sel_i[2]) begin`	`if (sel[2]) begin`
`hres <= s_dat_i[18:16];`	`hres <= dat[18:16];`
`vres <= s_dat_i[21:19];`	`vres <= dat[21:19];`
`end`	`end`
`if (s_sel_i[3]) begin`	`if (sel[3]) begin`
`page <= s_dat_i[24];`	`page <= dat[24];`
`pals <= s_dat_i[25];`	`pals <= dat[25];`
`end`	`end`
`if (\|s_sel_i[7:6]) map <= s_dat_i[59:48];`	`if (\|sel[7:6]) map <= dat[59:48];`
`end`	`end`
`REG_DISPLAYED:`	`REG_DISPLAYED:`
`begin`	`begin`
`if (\|s_sel_i[1:0]) hDisplayed <= s_dat_i[11:0];`	`if (\|sel[1:0]) hDisplayed <= dat[11:0];`
`if (\|s_sel_i[3:2]) vDisplayed <= s_dat_i[27:16];`	`if (\|sel[3:2]) vDisplayed <= dat[27:16];`
`if (\|s_sel_i[5:4]) hrefdelay <= s_dat_i[43:32];`	`if (\|sel[5:4]) hrefdelay <= dat[43:32];`
`if (\|s_sel_i[7:6]) vrefdelay <= s_dat_i[59:48];`	`if (\|sel[7:6]) vrefdelay <= dat[59:48];`
`end`	`end`
`REG_PAGE1ADDR: bm_base_addr1 <= s_dat_i;`	`REG_PAGE1ADDR: bm_base_addr1 <= dat;`
`REG_PAGE2ADDR: bm_base_addr2 <= s_dat_i;`	`REG_PAGE2ADDR: bm_base_addr2 <= dat;`
`REG_PXYZ:`	`REG_PXYZ:`
`begin`	`begin`
`if (\|s_sel_i[1:0]) px <= s_dat_i[11:0];`	`if (\|sel[1:0]) px <= dat[11:0];`
`if (\|s_sel_i[3:2]) py <= s_dat_i[27:16];`	`if (\|sel[3:2]) py <= dat[27:16];`
`if (\|s_sel_i[ 4]) pz <= s_dat_i[39:32];`	`if (\|sel[ 4]) pz <= dat[39:32];`
`end`	`end`
`REG_PCOLCMD:`	`REG_PCOLCMD:`
`begin`	`begin`
`if (s_sel_i[0]) pcmd <= s_dat_i[1:0];`	`if (sel[0]) pcmd <= dat[1:0];`
`if (s_sel_i[2]) raster_op <= s_dat_i[19:16];`	`if (sel[2]) raster_op <= dat[19:16];`
`if (\|s_sel_i[7:4]) color <= s_dat_i[63:32];`	`if (\|sel[7:4]) color <= dat[63:32];`
	`end`
	`REG_RASTCMP:`
	`begin`
	`if (sel[0]) rastcmp[7:0] <= dat[7:0];`
	`if (sel[1]) rastcmp[11:8] <= dat[11:8];`
	`if (sel[7]) rst_irq <= dat[63];`
`end`	`end`
`ifdef INTERNAL_SYNC_GEN	`ifdef INTERNAL_SYNC_GEN
`REG_TOTAL:`	`REG_TOTAL:`
`begin`	`begin`
`if (!sgLock) begin`	`if (!sgLock) begin`
`if (\|s_sel_i[1:0]) hTotal <= s_dat_i[11:0];`	`if (\|sel[1:0]) hTotal <= dat[11:0];`
`if (\|s_sel_i[3:2]) vTotal <= s_dat_i[27:16];`	`if (\|sel[3:2]) vTotal <= dat[27:16];`
`end`	`end`
`if (\|s_sel_i[7:4]) begin`	`if (\|sel[7:4]) begin`
`if (s_dat_i[63:32]==32'hA1234567)`	`if (dat[63:32]==32'hA1234567)`
`sgLock <= 1'b0;`	`sgLock <= 1'b0;`
`else if (s_dat_i[63:32]==32'h7654321A)`	`else if (dat[63:32]==32'h7654321A)`
`sgLock <= 1'b1;`	`sgLock <= 1'b1;`
`end`	`end`
`end`	`end`
`REG_SYNC_ONOFF:`	`REG_SYNC_ONOFF:`
`if (!sgLock) begin`	`if (!sgLock) begin`
`if (\|s_sel_i[1:0]) hSyncOff <= s_dat_i[11:0];`	`if (\|sel[1:0]) hSyncOff <= dat[11:0];`
`if (\|s_sel_i[3:2]) hSyncOn <= s_dat_i[27:16];`	`if (\|sel[3:2]) hSyncOn <= dat[27:16];`
`if (\|s_sel_i[5:4]) vSyncOff <= s_dat_i[43:32];`	`if (\|sel[5:4]) vSyncOff <= dat[43:32];`
`if (\|s_sel_i[7:6]) vSyncOn <= s_dat_i[59:48];`	`if (\|sel[7:6]) vSyncOn <= dat[59:48];`
`end`	`end`
`REG_BLANK_ONOFF:`	`REG_BLANK_ONOFF:`
`if (!sgLock) begin`	`if (!sgLock) begin`
`if (\|s_sel_i[1:0]) hBlankOff <= s_dat_i[11:0];`	`if (\|sel[1:0]) hBlankOff <= dat[11:0];`
`if (\|s_sel_i[3:2]) hBlankOn <= s_dat_i[27:16];`	`if (\|sel[3:2]) hBlankOn <= dat[27:16];`
`if (\|s_sel_i[5:4]) vBlankOff <= s_dat_i[43:32];`	`if (\|sel[5:4]) vBlankOff <= dat[43:32];`
`if (\|s_sel_i[7:6]) vBlankOn <= s_dat_i[59:48];`	`if (\|sel[7:6]) vBlankOn <= dat[59:48];`
`end`	`end`
`REG_BORDER_ONOFF:`	`REG_BORDER_ONOFF:`
`begin`	`begin`
`if (\|s_sel_i[1:0]) hBorderOff <= s_dat_i[11:0];`	`if (\|sel[1:0]) hBorderOff <= dat[11:0];`
`if (\|s_sel_i[3:2]) hBorderOn <= s_dat_i[27:16];`	`if (\|sel[3:2]) hBorderOn <= dat[27:16];`
`if (\|s_sel_i[5:4]) vBorderOff <= s_dat_i[43:32];`	`if (\|sel[5:4]) vBorderOff <= dat[43:32];`
`if (\|s_sel_i[7:6]) vBorderOn <= s_dat_i[59:48];`	`if (\|sel[7:6]) vBorderOn <= dat[59:48];`
`end`	`end`
`endif	`endif
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
`end`	`end`
`casez(s_adr_i[11:3])`	`casez(adri[11:3])`
`REG_CTRL:`	`REG_CTRL:`
`begin`	`begin`
`s_dat_o[0] <= onoff;`	`s_dat_o[0] <= onoff;`
`s_dat_o[10:8] <= color_depth;`	`s_dat_o[10:8] <= color_depth;`
`s_dat_o[11] <= greyscale;`	`s_dat_o[11] <= greyscale;`
Line 404...	Line 469...
`9'b10??_????_?: s_dat_o <= {32'h0,pal_wo};`	`9'b10??_????_?: s_dat_o <= {32'h0,pal_wo};`
`default: s_dat_o <= 64'd0;`	`default: s_dat_o <= 64'd0;`
`endcase`	`endcase`
`end`	`end`

`assign irq_o = 1'b0;`

`ifdef USE_CLOCK_GATE	`ifdef USE_CLOCK_GATE
`BUFHCE ucb1`	`BUFHCE ucb1`
`(`	`(`
`.I(dot_clk_i),`	`.I(dot_clk_i),`
`.CE(onoff),`	`.CE(onoff),`
Line 422...	Line 485...

`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
`// Horizontal and Vertical timing reference counters`	`// Horizontal and Vertical timing reference counters`
`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`	`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`

`wire pe_hsync, pe_hsync2;`
`wire pe_vsync;`
`edge_det edh1`	`edge_det edh1`
`(`	`(`
`.rst(rst_i),`	`.rst(rst_i),`
`.clk(vclk),`	`.clk(vclk),`
`.ce(1'b1),`	`.ce(1'b1),`
Line 502...	Line 563...
`BPP8: bpp = 7;`	`BPP8: bpp = 7;`
`BPP12: bpp = 11;`	`BPP12: bpp = 11;`
`BPP16: bpp = 15;`	`BPP16: bpp = 15;`
`BPP20: bpp = 19;`	`BPP20: bpp = 19;`
`BPP32: bpp = 31;`	`BPP32: bpp = 31;`
	`default: bpp = 15;`
`endcase`	`endcase`

`reg [5:0] shifts;`	`reg [5:0] shifts;`
`always @(color_depth)`	`always @(color_depth)`
	`case(MDW)`
	`128:`
	`case(color_depth)`
	`BPP4: shifts = 6'd32;`
	`BPP8: shifts = 6'd16;`
	`BPP12: shifts = 6'd10;`
	`BPP16: shifts = 6'd8;`
	`BPP20: shifts = 6'd6;`
	`BPP32: shifts = 6'd4;`
	`default: shifts = 6'd8;`
	`endcase`
	`64:`
`case(color_depth)`	`case(color_depth)`
`BPP4: shifts = 6'd16;`	`BPP4: shifts = 6'd16;`
`BPP8: shifts = 6'd8;`	`BPP8: shifts = 6'd8;`
`BPP12: shifts = 6'd5;`	`BPP12: shifts = 6'd5;`
`BPP16: shifts = 6'd4;`	`BPP16: shifts = 6'd4;`
`BPP20: shifts = 6'd3;`	`BPP20: shifts = 6'd3;`
`BPP32: shifts = 6'd2;`	`BPP32: shifts = 6'd2;`
`default: shifts = 6'd4;`	`default: shifts = 6'd4;`
`endcase`	`endcase`
	`32:`
	`case(color_depth)`
	`BPP4: shifts = 6'd8;`
	`BPP8: shifts = 6'd4;`
	`BPP12: shifts = 6'd2;`
	`BPP16: shifts = 6'd2;`
	`BPP20: shifts = 6'd1;`
	`BPP32: shifts = 6'd1;`
	`default: shifts = 6'd2;`
	`endcase`
	`default:`
	`begin`
	`$display("rtfBitmapController5: Bad master bus width");`
	`$finish;`
	`end`
	`endcase`

`wire vFetch = pixelRow < vDisplayed;`	`wire vFetch = pixelRow < vDisplayed;`
`wire fifo_rrst = pixelCol==12'hFFF;`	`wire fifo_rrst = pixelCol==12'hFFF;`
`wire fifo_wrst = pe_hsync2;`	`wire fifo_wrst = pe_hsync2;`

`wire[31:0] grAddr,xyAddr;`	`wire[31:0] grAddr,xyAddr;`
`reg [11:0] fetchCol;`	`reg [11:0] fetchCol;`
`wire [5:0] mb,me,ce;`	`localparam CMS = MDW==128 ? 6 : MDW==64 ? 5 : 4;`
`reg [63:0] mem_strip;`	`wire [CMS:0] mb,me,ce;`
`wire [63:0] mem_strip_o;`	`reg [MDW-1:0] mem_strip;`
	`wire [MDW-1:0] mem_strip_o;`
`wire [31:0] mem_color;`	`wire [31:0] mem_color;`

`gfx_CalcAddress6 u1`	`gfx_CalcAddress6 #(MDW) u1`
`(`	`(`
`.clk(m_clk_i),`	`.clk(m_clk_i),`
`.base_address_i(baseAddr),`	`.base_address_i(baseAddr),`
`.color_depth_i(color_depth),`	`.color_depth_i(color_depth),`
`.hdisplayed_i(hDisplayed),`	`.hdisplayed_i(hDisplayed),`
Line 541...	Line 632...
`.mb_o(),`	`.mb_o(),`
`.me_o(),`	`.me_o(),`
`.ce_o()`	`.ce_o()`
`);`	`);`

`gfx_CalcAddress6 u2`	`gfx_CalcAddress6 #(MDW) u2`
`(`	`(`
`.clk(m_clk_i),`	`.clk(m_clk_i),`
`.base_address_i(baseAddr),`	`.base_address_i(baseAddr),`
`.color_depth_i(color_depth),`	`.color_depth_i(color_depth),`
`.hdisplayed_i(hDisplayed),`	`.hdisplayed_i(hDisplayed),`
Line 602...	Line 693...
`do_loads <= 1'b1;`	`do_loads <= 1'b1;`
`else if (blankEdge)`	`else if (blankEdge)`
`do_loads <= 1'b0;`	`do_loads <= 1'b0;`

`assign m_stb_o = m_cyc_o;`	`assign m_stb_o = m_cyc_o;`
`assign m_sel_o = 8'hFF;`	`assign m_sel_o = MDW==128 ? 16'hFFFF : MDW==64 ? 8'hFF : 4'hF;`

`reg [31:0] adr;`	`reg [31:0] adr;`
`reg [3:0] state;`	`reg [3:0] state;`
`reg [127:0] icolor1;`	`reg [127:0] icolor1;`
`parameter IDLE = 4'd0;`	`parameter IDLE = 4'd0;`
Line 637...	Line 728...
`OPNAND: rastop = ~(a & b);`	`OPNAND: rastop = ~(a & b);`
`OPNOR: rastop = ~(a \| b);`	`OPNOR: rastop = ~(a \| b);`
`OPXNOR: rastop = ~(a ^ b);`	`OPXNOR: rastop = ~(a ^ b);`
`OPORN: rastop = a \| ~b;`	`OPORN: rastop = a \| ~b;`
`OPWHITE: rastop = 1'b1;`	`OPWHITE: rastop = 1'b1;`
	`default: rastop = 1'b0;`
`endcase`	`endcase`
`endfunction`	`endfunction`

`always @(posedge m_clk_i)`	`always @(posedge m_clk_i)`
`if (fifo_wrst)`	`if (fifo_wrst)`
Line 672...	Line 764...
`state <= IDLE;`	`state <= IDLE;`
`end`	`end`
`else`	`else`
`rstcmd <= 1'b1;`	`rstcmd <= 1'b1;`
`IDLE:`	`IDLE:`
`if (load_fifo) begin`	`if (load_fifo & ~m_ack_i) begin`
m_cyc_o <= `HIGH;	m_cyc_o <= `HIGH;
m_we_o <= `LOW;	m_we_o <= `LOW;
`m_adr_o <= adr;`	`m_adr_o <= adr;`
`state <= WAITLOAD;`	`state <= WAITLOAD;`
`end`	`end`
Line 694...	Line 786...
`end`	`end`
`LOADSTRIP:`	`LOADSTRIP:`
`if (m_ack_i) begin`	`if (m_ack_i) begin`
`wb_nack();`	`wb_nack();`
`mem_strip <= m_dat_i;`	`mem_strip <= m_dat_i;`
`icolor1 <= {32'b0,color} << mb;`	`icolor1 <= {96'b0,color} << mb;`
`rstcmd <= 1'b1;`	`rstcmd <= 1'b1;`
`if (pcmd==2'b01)`	`if (pcmd==2'b01)`
`state <= ICOLOR3;`	`state <= ICOLOR3;`
`else if (pcmd==2'b10)`	`else if (pcmd==2'b10)`
`state <= ICOLOR2;`	`state <= ICOLOR2;`
Line 721...	Line 813...
`rstcmd <= 1'b0;`	`rstcmd <= 1'b0;`
`end`	`end`
`// Registered inline color2mem`	`// Registered inline color2mem`
`ICOLOR2:`	`ICOLOR2:`
`begin`	`begin`
`for (n = 0; n < 64; n = n + 1)`	`for (n = 0; n < MDW; n = n + 1)`
`m_dat_o[n] <= (n >= mb && n <= me)`	`m_dat_o[n] <= (n >= mb && n <= me)`
`? ((n <= ce) ? rastop(raster_op, mem_strip[n], icolor1[n]) : icolor1[n])`	`? ((n <= ce) ? rastop(raster_op, mem_strip[n], icolor1[n]) : icolor1[n])`
`: mem_strip[n];`	`: mem_strip[n];`
`state <= STORESTRIP;`	`state <= STORESTRIP;`
`end`	`end`
Line 736...	Line 828...
`state <= ACKSTRIP;`	`state <= ACKSTRIP;`
`end`	`end`
`ACKSTRIP:`	`ACKSTRIP:`
`if (m_ack_i) begin`	`if (m_ack_i) begin`
`wb_nack();`	`wb_nack();`
`state <= pcmd == 2'b0 ? WAIT_NACK : WAITRST;`	`state <= pcmd == 2'b0 ? IDLE : WAITRST;`
`if (pcmd==2'b00)`	`if (pcmd==2'b00)`
`rstcmd <= 1'b0;`	`rstcmd <= 1'b0;`
`end`	`end`
`WAITLOAD:`	`WAITLOAD:`
`if (m_ack_i) begin`	`if (m_ack_i) begin`
`wb_nack();`	`wb_nack();`
`state <= WAIT_NACK;`	`state <= IDLE;`
	`// state <= WAIT_NACK;`
`end`	`end`
`WAIT_NACK:`	`WAIT_NACK:`
`if (~m_ack_i)`	`if (~m_ack_i)`
`state <= IDLE;`	`state <= IDLE;`
`default: state <= IDLE;`	`default: state <= IDLE;`
Line 761...	Line 854...
`end`	`end`
`endtask`	`endtask`

`reg [11:0] pixelColD1;`	`reg [11:0] pixelColD1;`
`reg [31:0] rgbo2,rgbo4;`	`reg [31:0] rgbo2,rgbo4;`
`reg [63:0] rgbo3;`	`reg [MDW-1:0] rgbo3;`
`always @(posedge vclk)`	`always @(posedge vclk)`
`case(color_depth)`	`case(color_depth)`
`BPP4: rgbo4 <= {rgbo3[3],7'h00,21'd0,rgbo3[2:0]}; // feeds into palette`	`BPP4: rgbo4 <= {rgbo3[3],7'h00,21'd0,rgbo3[2:0]}; // feeds into palette`
`BPP8: rgbo4 <= {rgbo3[7:6],6'h00,18'h0,rgbo3[5:0]}; // feeds into palette`	`BPP8: rgbo4 <= {rgbo3[7:6],6'h00,18'h0,rgbo3[5:0]}; // feeds into palette`
`BPP12: rgbo4 <= {rgbo3[11:9],5'd0,rgbo3[8:6],5'd0,rgbo3[5:3],5'd0,rgbo3[2:0],5'd0};`	`BPP12: rgbo4 <= {rgbo3[11:9],5'd0,rgbo3[8:6],5'd0,rgbo3[5:3],5'd0,rgbo3[2:0],5'd0};`
Line 797...	Line 890...

`// Before the hrefdelay expires, pixelCol will be negative, which is greater`	`// Before the hrefdelay expires, pixelCol will be negative, which is greater`
`// than hDisplayed as the value is unsigned. That means that fifo reading is`	`// than hDisplayed as the value is unsigned. That means that fifo reading is`
`// active only during the display area 0 to hDisplayed.`	`// active only during the display area 0 to hDisplayed.`
`wire shift1 = hc==hres;`	`wire shift1 = hc==hres;`
`reg [4:0] shift_cnt;`	`reg [5:0] shift_cnt;`
`always @(posedge vclk)`	`always @(posedge vclk)`
`if (pe_hsync)`	`if (pe_hsync)`
`shift_cnt <= 5'd1;`	`shift_cnt <= 5'd1;`
`else begin`	`else begin`
`if (shift1) begin`	`if (shift1) begin`
Line 829...	Line 922...
`always @(posedge vclk)`	`always @(posedge vclk)`
`if (rd_fifo)`	`if (rd_fifo)`
`rgbo3 <= rgbo1;`	`rgbo3 <= rgbo1;`
`else if (shift) begin`	`else if (shift) begin`
`case(color_depth)`	`case(color_depth)`
`BPP4: rgbo3 <= {4'h0,rgbo3[63:4]};`	`BPP4: rgbo3 <= {4'h0,rgbo3[MDW-1:4]};`
`BPP8: rgbo3 <= {8'h0,rgbo3[63:8]};`	`BPP8: rgbo3 <= {8'h0,rgbo3[MDW-1:8]};`
`BPP12: rgbo3 <= {12'h0,rgbo3[63:12]};`	`BPP12: rgbo3 <= {12'h0,rgbo3[MDW-1:12]};`
`BPP16: rgbo3 <= {16'h0,rgbo3[63:16]};`	`BPP16: rgbo3 <= {16'h0,rgbo3[MDW-1:16]};`
`BPP20: rgbo3 <= {20'h0,rgbo3[63:20]};`	`BPP20: rgbo3 <= {20'h0,rgbo3[MDW-1:20]};`
`BPP32: rgbo3 <= {32'h0,rgbo3[63:32]};`	`BPP32: rgbo3 <= {32'h0,rgbo3[MDW-1:32]};`
	`default: rgbo3 <= {16'h0,rgbo3[MDW-1:16]};`
`endcase`	`endcase`
`end`	`end`


`/* Debugging`	`/* Debugging`
Line 853...	Line 947...
`assign dat[95:84] = pixelRow[7] ? 12'hEA4 : 12'h000;`	`assign dat[95:84] = pixelRow[7] ? 12'hEA4 : 12'h000;`
`assign dat[107:96] = pixelRow[8] ? 12'hEA4 : 12'h000;`	`assign dat[107:96] = pixelRow[8] ? 12'hEA4 : 12'h000;`
`assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;`	`assign dat[119:108] = pixelRow[9] ? 12'hEA4 : 12'h000;`
`*/`	`*/`

`rtfVideoFifo3 #(64) uf1`	`rtfVideoFifo3 #(MDW) uf1`
`(`	`(`
`.wrst(fifo_wrst),`	`.wrst(fifo_wrst),`
`.wclk(m_clk_i),`	`.wclk(m_clk_i),`
`.wr(m_ack_i && state==WAITLOAD),`	`.wr(m_ack_i && state==WAITLOAD),`
`.di(m_dat_i),`	`.di(m_dat_i),`

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[/] [rtfbitmapcontroller/] [trunk/] [rtl/] [verilog/] [rtfBitmapController5.v] - Diff between revs 23 and 24