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https://opencores.org/ocsvn/rtfbitmapcontroller/rtfbitmapcontroller/trunk
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Rev 23 |
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2008-2015 Robert Finch, Stratford
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// \\__/ o\ (C) 2008-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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//
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//
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// Verilog 1995
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// Verilog 1995
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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module rtfVideoFifo3(wrst, wclk, wr, di, rrst, rclk, rd, dout, cnt);
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module rtfVideoFifo3(wrst, wclk, wr, di, rrst, rclk, rd, dout, cnt);
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parameter WID=128;
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input wrst;
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input wrst;
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input wclk;
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input wclk;
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input wr;
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input wr;
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input [127:0] di;
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input [WID-1:0] di;
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input rrst;
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input rrst;
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input rclk;
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input rclk;
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input rd;
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input rd;
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output [127:0] dout;
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output [WID-1:0] dout;
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output [7:0] cnt;
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output [7:0] cnt;
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reg [7:0] cnt;
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reg [7:0] cnt;
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reg [7:0] wr_ptr;
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reg [7:0] wr_ptr;
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reg [7:0] rd_ptr,rrd_ptr;
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reg [7:0] rd_ptr,rrd_ptr;
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reg [127:0] mem [0:255];
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reg [WID-1:0] mem [0:255];
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wire [7:0] wr_ptr_p1 = wr_ptr + 8'd1;
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wire [7:0] wr_ptr_p1 = wr_ptr + 8'd1;
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wire [7:0] rd_ptr_p1 = rd_ptr + 8'd1;
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wire [7:0] rd_ptr_p1 = rd_ptr + 8'd1;
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reg [7:0] rd_ptrs;
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reg [7:0] rd_ptrs;
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