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/* ============================================================================
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// ============================================================================
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2006,2007,2011 Robert T Finch
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// __
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robfinch@<remove>sympatico.ca
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// \\__/ o\ (C) 2006-2020 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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ParallelToSerial.v
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// \/_// robfinch<remove>@finitron.ca
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Parallel to serial data converter (shift register).
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// ||
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//
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This source code is available for evaluation and validation purposes
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//
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only. This copyright statement and disclaimer must remain present in
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// ParallelToSerial.v
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the file.
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// Parallel to serial data converter (shift register).
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//
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// BSD 3-Clause License
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NO WARRANTY.
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// Redistribution and use in source and binary forms, with or without
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THIS Work, IS PROVIDEDED "AS IS" WITH NO WARRANTIES OF ANY KIND, WHETHER
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// modification, are permitted provided that the following conditions are met:
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EXPRESS OR IMPLIED. The user must assume the entire risk of using the
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//
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Work.
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// 1. Redistributions of source code must retain the above copyright notice, this
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// list of conditions and the following disclaimer.
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IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
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//
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INCIDENTAL, CONSEQUENTIAL, OR PUNITIVE DAMAGES WHATSOEVER RELATING TO
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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THE USE OF THIS WORK, OR YOUR RELATIONSHIP WITH THE AUTHOR.
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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IN ADDITION, IN NO EVENT DOES THE AUTHOR AUTHORIZE YOU TO USE THE WORK
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//
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IN APPLICATIONS OR SYSTEMS WHERE THE WORK'S FAILURE TO PERFORM CAN
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// 3. Neither the name of the copyright holder nor the names of its
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REASONABLY BE EXPECTED TO RESULT IN A SIGNIFICANT PHYSICAL INJURY, OR IN
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// contributors may be used to endorse or promote products derived from
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LOSS OF LIFE. ANY SUCH USE BY YOU IS ENTIRELY AT YOUR OWN RISK, AND YOU
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// this software without specific prior written permission.
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AGREE TO HOLD THE AUTHOR AND CONTRIBUTORS HARMLESS FROM ANY CLAIMS OR
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//
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LOSSES RELATING TO SUCH UNAUTHORIZED USE.
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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Webpack 9.1i xc3s1000-4ft256
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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LUTs / slices / MHz
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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block rams
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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============================================================================ */
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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module ParallelToSerial(rst, clk, ce, ld, qin, d, qh);
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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parameter WID=8;
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//
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// ============================================================================
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//
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module ParallelToSerial(rst, clk, ce, ld, a, qin, d, qh);
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localparam WID=64;
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input rst; // reset
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input rst; // reset
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input clk; // clock
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input clk; // clock
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input ce; // clock enable
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input ce; // clock enable
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input ld; // load
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input ld; // load
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input [2:0] a; // bits 3-5 of the font width
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input qin; // serial shifting input
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input qin; // serial shifting input
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input [WID:1] d; // data to load
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input [WID-1:0] d; // data to load
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output qh; // serial output
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output reg qh; // serial output
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reg [WID:1] q;
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reg [WID-1:0] q;
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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q <= 0;
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q <= {WID{1'b0}};
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else if (ce) begin
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else if (ce) begin
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if (ld)
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if (ld)
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q <= d;
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q <= d;
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else
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else
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q <= {q[WID-1:1],qin};
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q <= {q[WID-2:0],qin};
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end
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end
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assign qh = q[WID];
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always @(posedge clk)
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if (ce)
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casez(a)
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3'b1??: qh <= q[63];
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// 3'b110: qh <= q[55];
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// 3'b101: qh <= q[47];
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// 3'b100: qh <= q[39];
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3'b01?: qh <= q[31];
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// 3'b010: qh <= q[23];
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3'b001: qh <= q[15];
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3'b000: qh <= q[ 7];
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endcase
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endmodule
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endmodule
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