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https://opencores.org/ocsvn/rtftextcontroller/rtftextcontroller/trunk
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Rev 27 |
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Line 1... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2006-2014 Robert Finch, Stratford
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// \\__/ o\ (C) 2006-2016 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// rtfTextController3.v
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// rtfTextController3.v
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Line 155... |
wire [27:0] tdat_o;
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wire [27:0] tdat_o;
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wire [8:0] chdat_o;
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wire [8:0] chdat_o;
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wire [2:0] scanindex = scanline[2:0];
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wire [2:0] scanindex = scanline[2:0];
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Address Decoding
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// Address Decoding
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// I/O range Dx
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// I/O range Dx
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//--------------------------------------------------------------------
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//--------------------------------------------------------------------
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wire cs_text = cyc_i && stb_i && (adr_i[31:16]==pTextAddress[31:16]);
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wire cs_text = cyc_i && stb_i && (adr_i[31:16]==pTextAddress[31:16]);
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cursorStart <= 5'd00;
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cursorStart <= 5'd00;
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cursorEnd <= 5'd31;
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cursorEnd <= 5'd31;
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cursorPos <= 16'h0003;
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cursorPos <= 16'h0003;
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cursorType <= 2'b00;
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cursorType <= 2'b00;
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txtTcCode <= 9'h1ff;
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txtTcCode <= 9'h1ff;
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charOutDelay <= 12'd2;
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charOutDelay <= 12'd3;
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end
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end
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else if (num==4'd2) begin
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else if (num==4'd2) begin
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windowTop <= 12'd64;//12'd16;
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windowTop <= 12'd64;//12'd16;
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windowLeft <= 12'h376;//12'd86;
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windowLeft <= 12'h376;//12'd86;
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pixelWidth <= 4'd0; // 680 pixels
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pixelWidth <= 4'd0; // 680 pixels
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cursorStart <= 5'd00;
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cursorStart <= 5'd00;
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cursorEnd <= 5'd31;
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cursorEnd <= 5'd31;
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cursorPos <= 16'h0003;
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cursorPos <= 16'h0003;
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cursorType <= 2'b00;
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cursorType <= 2'b00;
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txtTcCode <= 9'h1ff;
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txtTcCode <= 9'h1ff;
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charOutDelay <= 12'd2;
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charOutDelay <= 12'd3;
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end
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end
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end
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end
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else begin
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else begin
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if (cs_reg & we_i) begin // register write ?
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if (cs_reg & we_i) begin // register write ?
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